- Patent Title: Adaptive hardware transactional memory based concurrency control
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Application No.: US16367910Application Date: 2019-03-28
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Publication No.: US11947994B2Publication Date: 2024-04-02
- Inventor: Thomas Legler
- Applicant: SAP SE
- Applicant Address: DE Walldorf
- Assignee: SAP SE
- Current Assignee: SAP SE
- Current Assignee Address: DE Walldorf
- Agency: Mintz Levin Cohn Ferris Glovsky and Popeo, P.C.
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F9/52 ; G06F12/0817 ; G06F16/25

Abstract:
A method may include determining a threshold quantity of attempts to optimistically perform a first transaction operating data stored in a database. The threshold quantity of attempts may be determined based on an expected workload of the first transaction and/or a workload at the database. The first transaction may be performed optimistically including by tracking cache lines accessed by the first transaction and detecting, based on a second transaction writing to a cache line accessed by the first transaction, a conflict between the first transaction and the second transaction. If the first transaction is not successful performed after the threshold quantity of attempts to optimistically perform the first transaction, the first transaction may be performed in a fallback mode including by acquiring a lock to prevent the second transaction from accessing a same data in the database as the first transaction. Related systems and articles of manufacture are also provided.
Public/Granted literature
- US20200310862A1 ADAPTIVE HARDWARE TRANSACTIONAL MEMORY BASED CONCURRENCY CONTROL Public/Granted day:2020-10-01
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