Invention Grant
- Patent Title: Semiconductor device and method of forming vertical interconnect structure for PoP module
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Application No.: US17347065Application Date: 2021-06-14
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Publication No.: US11955467B2Publication Date: 2024-04-09
- Inventor: Junghwan Jang , Giwoong Nam , Myongsuk Kang
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: PATENT LAW GROUP: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L25/10
- IPC: H01L25/10 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L23/00 ; H01L23/31 ; H01L23/538 ; H01L25/00

Abstract:
A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.
Public/Granted literature
- US20220399315A1 Semiconductor Device and Method of Forming Vertical Interconnect Structure for POP Module Public/Granted day:2022-12-15
Information query
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