Invention Grant
- Patent Title: Passivation layers for thin film transistors and methods of fabrication
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Application No.: US16914172Application Date: 2020-06-26
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Publication No.: US11955560B2Publication Date: 2024-04-09
- Inventor: Abhishek A. Sharma , Arnab Sen Gupta , Travis W. LaJoie , Sarah Atanasov , Chieh-Jen Ku , Bernhard Sell , Noriyuki Sato , Van Le , Matthew Metz , Hui Jae Yoo , Pei-Hua Wang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patent Group, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/22 ; H01L29/786 ; H10B61/00 ; H10B63/00

Abstract:
A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
Public/Granted literature
- US20210408291A1 PASSIVATION LAYERS FOR THIN FILM TRANSISTORS AND METHODS OF FABRICATION Public/Granted day:2021-12-30
Information query
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