Vertical heterostructure semiconductor memory cell and methods for making the same

Invention Grant

US11956940B2 Vertical heterostructure semiconductor memory cell and methods for making the same 有权

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Patent Title: Vertical heterostructure semiconductor memory cell and methods for making the same
Application No.: US18102758

Application Date: 2023-01-29
Publication No.: US11956940B2

Publication Date: 2024-04-09
Inventor: Gerben Doornbos , Marcus Johannes Henricus Van Dal
Applicant: Taiwan Semiconductor Manufacturing Company Limited
Applicant Address: TW Hsinchu
Assignee: Taiwan Semiconductor Manufacturing Company Limited
Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
Current Assignee Address: TW Hsinchu
Agency: The Marbury Law Group, PLLC
Main IPC: H10B12/00
IPC: H10B12/00 ; H01L29/06 ; H01L29/225 ; H01L29/66 ; H01L29/78 ; H01L29/786

Vertical heterostructure semiconductor memory cell and methods for making the same

Abstract:

A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.

Public/Granted literature

US20230171937A1 VERTICAL HETEROSTRUCTURE SEMICONDUCTOR MEMORY CELL AND METHODS FOR MAKING THE SAME Public/Granted day:2023-06-01

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