Invention Publication
- Patent Title: VERTICAL HETEROSTRUCTURE SEMICONDUCTOR MEMORY CELL AND METHODS FOR MAKING THE SAME
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Application No.: US18102758Application Date: 2023-01-29
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Publication No.: US20230171937A1Publication Date: 2023-06-01
- Inventor: Gerben DOORNBOS , Marcus Johannes Henricus VAN DAL
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Main IPC: H10B12/00
- IPC: H10B12/00 ; H01L29/786 ; H01L29/78 ; H01L29/66 ; H01L29/225 ; H01L29/06
Abstract:
A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.
Public/Granted literature
- US11956940B2 Vertical heterostructure semiconductor memory cell and methods for making the same Public/Granted day:2024-04-09
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