Invention Grant
- Patent Title: Method and system for continuously verifying integrity of secure instructions during runtime
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Application No.: US17125208Application Date: 2020-12-17
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Publication No.: US12001557B2Publication Date: 2024-06-04
- Inventor: Taimour Wehbe , Marc Adas
- Applicant: RENESAS ELECTRONICS AMERICA INC.
- Applicant Address: US CA Milpitas
- Assignee: Renesas Electronics America Inc.
- Current Assignee: Renesas Electronics America Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Foley & Lardner LLP
- Main IPC: G06F21/57
- IPC: G06F21/57 ; H04L9/32

Abstract:
Example implementations include a method of requesting an instruction block associated with one or more instructions and located at one or more addresses of a system memory, obtaining the instruction block from the system memory, generating a hash of the instruction block, obtaining an expected hash associated with the instruction block, comparing the expected hash with the generated hash, in accordance with a determination that the expected hash matches the generated hash, generating a first validation response associated with the instruction block. Example implementations also include a method of obtaining a secure instruction image including an expected hash associated with an instruction block, the instruction block associated with one or more instructions and located at one or more addresses of a system memory, storing the secure instruction image at a configuration register, and enabling the hardware controller to perform one or more hashing operations associated with the instruction block during runtime of a system processor.
Public/Granted literature
- US20210200873A1 METHOD AND SYSTEM FOR CONTINUOUSLY VERIFYING INTEGRITY OF SECURE INSTRUCTIONS DURING RUNTIME Public/Granted day:2021-07-01
Information query