Invention Grant
- Patent Title: Systems and methods for reducing instruction code memory footprint for multiple processes executed at a coprocessor
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Application No.: US16719076Application Date: 2019-12-18
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Publication No.: US12086447B2Publication Date: 2024-09-10
- Inventor: Khaled Hamidouche , Michael W. Lebeane , Hari S. Thangirala
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/0882

Abstract:
A processing system includes a first processor couplable to a first memory and a second memory. In response to a page migration trigger for a page in the first memory, the first processor is configured to, responsive to the page being a read-only page storing code for execution, initiate migration of the page to a code cache portion of a second memory associated with a second processor and shared by multiple processes executing at the second processor, and to configure each process of a set of processes executing at the second processor to access and execute the code from the code cache portion.
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