Invention Grant
- Patent Title: Double-patterning method to improve sidewall uniformity
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Application No.: US17326334Application Date: 2021-05-21
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Publication No.: US12106964B2Publication Date: 2024-10-01
- Inventor: Chu-Chun Hsieh , Ting-Wei Wu , Chih-Jung Ni
- Applicant: Winbond Electronics Corp.
- Applicant Address: TW Taichung
- Assignee: Winbond Electronics Corp.
- Current Assignee: Winbond Electronics Corp.
- Current Assignee Address: TW Taichung
- Agency: JCIPRNET
- Priority: TW 9120246 2020.06.16
- Main IPC: H01L21/033
- IPC: H01L21/033

Abstract:
Provided is a patterning method including following steps. A doped polysilicon layer, a core layer, and an undoped polysilicon layer are sequentially formed on a target layer. The undoped polysilicon layer is patterned to form a polysilicon pattern. A first etching process is performed by using the polysilicon pattern as a mask to remove a portion of the core layer to form a core pattern. A second etching process is performed to remove the polysilicon pattern. An atomic layer deposition (ALD) process is performed to form a spacer material on the core pattern and the doped polysilicon layer. A portion of the spacer material is removed to form a spacer on a sidewall of the core pattern. A portion of the core pattern and an underlying doped polysilicon are removed.
Public/Granted literature
- US20210391174A1 PATTERNING METHOD Public/Granted day:2021-12-16
Information query
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