A memory device includes a memory cell array connected to a first word line, a pair of second word lines, and a bit line and configured to perform a multiply-accumulate (MAC) operation depending on a ternary input provided from the pair of second word lines and a binary weight preset based on the first word line and the bit line; a peripheral circuit configured to control the memory cell array; and an ADC (analog-to-digital converter) circuit configured to convert a voltage value dependent on the MAC operation into a digital value.