Invention Grant
- Patent Title: Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications
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Application No.: US16713684Application Date: 2019-12-13
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Publication No.: US12249622B2Publication Date: 2025-03-11
- Inventor: Tanuj Trivedi , Rahul Ramaswamy , Jeong Dong Kim , Ting Chang , Walid M. Hafez , Babak Fallahazad , Hsu-Yu Chang , Nidhi Nidhi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; B82Y40/00

Abstract:
Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. In an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. The first semiconductor layers may have a first spacing. In an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. The semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. In an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.
Public/Granted literature
- US20210184001A1 NANORIBBON THICK GATE DEVICES WITH DIFFERENTIAL RIBBON SPACING AND WIDTH FOR SOC APPLICATIONS Public/Granted day:2021-06-17
Information query
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