公开(公告)号：US11563000B2

公开(公告)日：2023-01-24

申请号：US16830120

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Chia-Hong Jan

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.

公开(公告)号：US10164115B2

公开(公告)日：2018-12-25

申请号：US15127850

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Neville L. Dias ,  Chia-Hong Jan ,  Walid M. Hafez ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu

IPC: H01L29/78 ,  H03D7/14 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12 ,  H03D7/16 ,  H01L29/417

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

公开(公告)号：US12040395B2

公开(公告)日：2024-07-16

申请号：US16713648

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Ting Chang ,  Babak Fallahazad ,  Tanuj Trivedi ,  Jeong Dong Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7816 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.

公开(公告)号：US11862703B2

公开(公告)日：2024-01-02

申请号：US17870401

申请日：2022-07-21

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Ting Chang ,  Nidhi Nidhi ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/42392 ,  H01L21/02532 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1062 ,  H01L29/165 ,  H01L29/66795

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US11581404B2

公开(公告)日：2023-02-14

申请号：US17308900

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Jeong Dong Kim ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Rahul Ramaswamy ,  Ting Chang ,  Babak Fallahazad

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/285

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

公开(公告)号：US10811751B2

公开(公告)日：2020-10-20

申请号：US16461554

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Chia-Hong Jan ,  Walid Hafez ,  Neville Dias ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Chen-Guan Lee

IPC: H01P3/12 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/66 ,  H01P3/127 ,  H01P5/12 ,  H01P11/00

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.

公开(公告)号：US10340273B2

公开(公告)日：2019-07-02

申请号：US15409435

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L Dias ,  Chanaka D Munasinghe

IPC: H01L27/092 ,  H01L21/82 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US20250120143A1

公开(公告)日：2025-04-10

申请号：US18482192

申请日：2023-10-06

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Adam Brand ,  Chen-Guan Lee ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Adithya Shankar ,  Marko Radosavljevic

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: Described herein are gate-all-around (GAA) transistors with extended drains, where the drain region extends through a well region below the GAA transistor. A high voltage can be applied to the drain, and the extended drain region provides a voltage drop. The transistor length (and, specifically length of the extended drain) can be varied based on the input voltage to the device, e.g., providing a longer drain for higher input voltages. The extended drain transistors can be implemented in devices that include CFETs, either by implementing the extended drain transistor across both CFET layers, or by providing a sub-fin pedestal with the well regions in the lower layer.

公开(公告)号：US11094782B1

公开(公告)日：2021-08-17

申请号：US16795081

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Jeong Dong Kim ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Rahul Ramaswamy ,  Ting Chang ,  Babak Fallahazad

IPC: H01L29/06 ,  H01L29/10 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

公开(公告)号：US10559688B2

公开(公告)日：2020-02-11

申请号：US16081215

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Chen-Guan Lee ,  Walid M. Hafez ,  Joodong Park ,  Chia-Hong Jan ,  Hsu-Yu Chang

IPC: H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.