Invention Grant
- Patent Title: Sideways vias in isolation areas to contact interior layers in stacked devices
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Application No.: US18419015Application Date: 2024-01-22
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Publication No.: US12255137B2Publication Date: 2025-03-18
- Inventor: Ehren Mannebach , Aaron Lilak , Hui Jae Yoo , Patrick Morrow , Anh Phan , Willy Rachmady , Cheng-Ying Huang , Gilbert Dewey , Rishabh Mehandru
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/8234 ; H01L25/16 ; H01L29/06

Abstract:
Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
Public/Granted literature
- US20240162141A1 SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES Public/Granted day:2024-05-16
Information query
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