Invention Grant
- Patent Title: Semiconductor device on wiring board having reference potential planes with openings
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Application No.: US17743033Application Date: 2022-05-12
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Publication No.: US12278198B2Publication Date: 2025-04-15
- Inventor: Yoshikazu Tanaka , Tadashi Kameyama , Takafumi Betsui
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Rimon P.C.
- Main IPC: H01L23/66
- IPC: H01L23/66 ; H01P3/08

Abstract:
A semiconductor device includes a semiconductor package having a differential signal terminal pair, and a wiring board. The wiring board includes a first and a second signal transmission line and a reference potential plane. The first and the second signal transmission line is formed in a first conductive layer and connected to the differential signal terminal pair. The reference potential plane includes a conductive pattern formed in a different conductive layer from the first conductive layer. The conductive pattern includes a first and a second region overlapped with the first and the second signal transmission line in plan view, respectively. The conductive pattern has a plurality of openings in the first and the second region. An area of a first conductive portion of the reference potential plane in the first region becomes equal to an area of a second conductive portion of the reference potential plane in the second region.
Public/Granted literature
- US20230369257A1 SEMICONDUCTOR DEVICE Public/Granted day:2023-11-16
Information query
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