Invention Grant
- Patent Title: Three-dimensional memory device with divided drain select gate lines and method for forming the same
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Application No.: US17568630Application Date: 2022-01-04
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Publication No.: US12302560B2Publication Date: 2025-05-13
- Inventor: Di Wang , Yan Gu , Zhiliang Xia , Wenxi Zhou , Zongliang Huo
- Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Applicant Address: CN Wuhan
- Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee Address: CN Wuhan
- Agency: BAYES PLLC
- Main IPC: H10B43/20
- IPC: H10B43/20 ; H01L21/28 ; H01L29/423 ; H01L29/49 ; H10D30/69 ; H10D64/01 ; H10D64/66

Abstract:
A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.
Public/Granted literature
- US20230189521A1 THREE-DIMENSIONAL MEMORY DEVICE WITH DIVIDED DRAIN SELECT GATE LINES AND METHOD FOR FORMING THE SAME Public/Granted day:2023-06-15
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