公开(公告)号：US20250015156A1

公开(公告)日：2025-01-09

申请号：US18396543

申请日：2023-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong Zhang ,  Qingfu Zhang ,  Di Wang ,  Wenxi Zhou

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H10B41/27 ,  H10B43/27

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stacked layer and a top select gate layer located on the stacked layer. The semiconductor device may include a gate-line structure extending through the top select gate layer and the stacked layer. A portion of the gate-line structure that extends through the top select gate layer may be a first isolation structure, and the first isolation structure may include a contact layer in contact with the top select gate layer. The semiconductor device may include a channel structure extending through the stacked layer and a first dielectric layer located on the top select gate layer, where the first dielectric layer and the contact layer comprise different insulating materials. The semiconductor device may include a channel local contact extending through the first dielectric layer and corresponding to the channel structure.

公开(公告)号：US12193230B2

公开(公告)日：2025-01-07

申请号：US17459456

申请日：2021-08-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Bingjie Yan ,  Di Wang ,  Cuicui Kong ,  Wenxi Zhou

IPC: H01L27/11582 ,  H10B43/27

Abstract: A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers formed on the doped semiconductor layer. The conductive layers include a plurality of word lines, and a drain select gate line. The channel structure extends through the stack structure along a first direction and is in contact with the doped semiconductor layer. The drain select gate line includes a first dielectric layer in contact with the channel structure, and a first polysilicon layer in contact with the first dielectric layer.

公开(公告)号：US12094767B2

公开(公告)日：2024-09-17

申请号：US17580051

申请日：2022-01-20

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Ling Xu ,  Di Wang ,  Zhong Zhang ,  Wenxi Zhou

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/76832 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/535

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a staircase structure and a dividing wall in the alternating dielectric stack. The staircase structure and the dividing wall extend in a second direction parallel to the substrate, and the dividing wall is adjacent to the staircase structure. The method also includes forming, sequentially on the staircase structure, a first barrier layer and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the dividing wall. The GLS opening penetrates through the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction that is parallel to the substrate and is perpendicular to the second direction.

公开(公告)号：US20240206181A1

公开(公告)日：2024-06-20

申请号：US18090915

申请日：2022-12-29

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Di Wang ,  Yuancheng Yang ,  Lei Liu ,  Tao Yang ,  Kun Zhang ,  Dongxue Zhao ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H10B43/40 ,  H01L23/528 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

Abstract: A memory device includes a semiconductor layer; a peripheral circuit disposed on the semiconductor layer; and an array of memory cells disposed aside the peripheral circuit on the semiconductor layer. Each of the memory cells includes a semiconductor body extending in a first direction, a first end of the semiconductor body is in contact with the semiconductor layer; a word line gate extending in a second direction perpendicular to the first direction; a plate line gate extending in the second direction; and a dielectric layer disposed between the semiconductor body and the word line gate and the plate line gate.

公开(公告)号：US20240107761A1

公开(公告)日：2024-03-28

申请号：US17968595

申请日：2022-10-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Di Wang ,  Zhong Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo ,  Wei Xie

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

公开(公告)号：US20230413542A1

公开(公告)日：2023-12-21

申请号：US17843674

申请日：2022-06-17

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Ling Xu ,  Zhong Zhang ,  Wenxi Zhou ,  Di Wang ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/11556 ,  H01L27/11521

CPC classification number: H01L27/11556 ,  H01L27/11521

Abstract: A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device also includes a plurality of landing structures each over a respective conductive layer at a respective stair. Each of the landing structures includes a first layer having a first material and a second layer having a second material, the first layer being over the second layer.

公开(公告)号：US20230189516A1

公开(公告)日：2023-06-15

申请号：US17648783

申请日：2022-01-24

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao Yang ,  DongXue Zhao ,  Yuancheng Yang ,  Lei Liu ,  Kun Zhang ,  Di Wang ,  Wenxi Zhou ,  ZhiLiang Xia ,  ZongLiang Huo

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/532

CPC classification number: H01L27/11556 ,  G11C5/025 ,  H01L27/11582 ,  H01L23/53204

Abstract: The present disclosure is directed to a memory structure including a staircase structure. The staircase structure can include a bottom select gate, a plate line formed above the bottom select gate, and a word line formed above the plate line. The pillar can extend through the bottom select gate, the plate line, and the word line. The memory structure can also include a source structure formed under the pillar and a drain cap formed above the pillar. The memory structure can further include a bit line formed above the drain cap.

公开(公告)号：US20230142290A1

公开(公告)日：2023-05-11

申请号：US17646549

申请日：2021-12-30

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： DongXue ZHAO ,  Tao Yang ,  Yuancheng Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  ZongLiang Huo

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.

公开(公告)号：US20230056340A1

公开(公告)日：2023-02-23

申请号：US17570091

申请日：2022-01-06

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Xie ,  Di Wang ,  Bingguo Wang ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.

公开(公告)号：US11450604B2

公开(公告)日：2022-09-20

申请号：US16944835

申请日：2020-07-31

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Di Wang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L23/522 ,  G11C8/14 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure. The staircase structure includes a plurality of stairs extending along the lateral direction, and a bridge structure in contact with the first memory array structure and the second memory array structure. The plurality of stairs includes a stair above one or more dielectric pairs The stair includes a conductor portion on a top surface of the stair and in contact with and electrically connected to the bridge structure, and is electrically connected to at least one of a first memory array structure and a second memory array structure of the memory array structure through the bridge structure. Along a second lateral direction, a width of the conductor portion is unchanged.