Invention Grant
- Patent Title: Lithographically defined vertical interconnect access (VIA) for a bridge die first level interconnect (FLI)
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Application No.: US16455688Application Date: 2019-06-27
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Publication No.: US12334447B2Publication Date: 2025-06-17
- Inventor: Kristof Darmawikarta , Tarek Ibrahim , Siddharth Alur , Rahul Jain , Haobo Chen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Haley Guiliano LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L23/00 ; H01L23/538

Abstract:
Embodiments described herein relate to lithographically defined vertical interconnect accesses (litho-vias) for a bridge die first level interconnect (FLI) and techniques of fabricating such litho-vias. In one example, a package substrate comprises a bridge die embedded in the package substrate; a first contact pad outside a perimeter of the bridge die; a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via; a third pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a second via. The first contact pad has a surface finish disposed thereon. A first protruded interconnect structure is positioned on the first via and a second protruded interconnect structure is positioned on the second via. Each of the first and second vias have sidewalls that are substantially vertical.
Information query
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