Invention Application
- Patent Title: Process for reducing extraneous metal plating
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Application No.: US09917701Application Date: 2001-07-31
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Publication No.: US20010040047A1Publication Date: 2001-11-15
- Inventor: John Joseph Konrad , Konstantinos I. Papathomas , Timothy Leroy Wells , James Warren Wilson
- Main IPC: H05K001/00
- IPC: H05K001/00 ; B05D005/12 ; H02B001/24

Abstract:
Printed circuit boards, cards and chip carriers are fabricated by treating an already circuitized substrate with a swelling agent, then treating the circuitized substrate with a composition containing an alkaline permanganate, a chromate and/or chlorite and then applying a metal layer to coat the circuitized portion of the substrate.
Public/Granted literature
- US06455139B2 Process for reducing extraneous metal plating Public/Granted day:2002-09-24
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