Invention Application
- Patent Title: METHOD FOR FABRICATING A MICROELECTRONIC DEVICE USING WAFER-LEVEL ADHESION LAYER DEPOSITION
- Patent Title (中): 使用水平粘合层沉积制造微电子器件的方法
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Application No.: US09903025Application Date: 2001-07-11
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Publication No.: US20030013232A1Publication Date: 2003-01-16
- Inventor: Steven Towle , Hajime Sakamoto , Dongdong Wang
- Applicant: Intel Corporation
- Applicant Address: null
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: null
- Main IPC: H01L021/44
- IPC: H01L021/44 ; H01L021/48

Abstract:
A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.
Public/Granted literature
- US06586276B2 Method for fabricating a microelectronic device using wafer-level adhesion layer deposition Public/Granted day:2003-07-01
Information query