公开(公告)号：US20030045083A1

公开(公告)日：2003-03-06

申请号：US09946749

申请日：2001-09-05

Applicant: Intel Corporation

Inventor： Steven Towle ,  John Tang ,  John S. Cuendet ,  Henning Braunisch ,  Thomas S. Dory

IPC: H01L021/44

CPC classification number: H01L23/5389 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15173 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A low cost microelectronic circuit package includes a single build up metallization layer above a microelectronic die. At least one die is fixed within a package core using, for example, an encapsulation material. A single metallization layer is then built up over the die/core assembly. The metallization layer includes a number of landing pads having a pitch that allows the microelectronic device to be directly mounted to an external circuit board. In one embodiment, the metallization layer includes a number of signal landing pads within a peripheral region of the layer and at least one power landing pad and one ground landing pad toward a central region of the layer.

Abstract translation: 低成本微电子电路封装包括在微电子管芯上方的单个堆积金属化层。 使用例如封装材料将至少一个管芯固定在封装芯内。 然后在模具/芯组件上构建单个金属化层。 金属化层包括许多具有允许微电子器件直接安装到外部电路板的间距的着陆焊盘。 在一个实施例中，金属化层包括在该层的外围区域内的多个信号着陆焊盘以及朝向该层的中心区域的至少一个电源着陆焊盘和一个接地焊盘。

公开(公告)号：US20030227077A1

公开(公告)日：2003-12-11

申请号：US10424383

申请日：2003-04-28

Applicant: Intel Corporation

Inventor： Steven Towle ,  Paul H. Wermer

IPC: H01L023/02

CPC classification number: H01L21/568 ,  H01L23/142 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4614 ,  H01L2924/00

Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.

公开(公告)号：US20020173133A1

公开(公告)日：2002-11-21

申请号：US09861689

申请日：2001-05-21

Applicant: Intel Corporation

Inventor： Steven Towle ,  Martha Jones ,  Quat T. Vu

IPC: H01L021/44

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Expanded bond pads are formed over a passivation layer on a semiconductor wafer before the wafer is diced into individual circuit chips. After dicing, the individual chips are packaged by fixing each chip within a package core and building up one or more metallization layers on the resulting assembly. In at least one embodiment, a high melting temperature (lead free) alternative bump metallurgy (ABM) form of controlled collapse chip connect (C4) processing is used to form relatively wide conducting platforms over the bond pads on the wafer.

Abstract translation: 在将晶片切割成单独的电路芯片之前，在半导体晶片上的钝化层上形成扩展焊盘。 在切割之后，通过将每个芯片固定在封装芯中并在所得组件上建立一个或多个金属化层来封装各个芯片。 在至少一个实施例中，使用可控崩溃芯片连接（C4）处理的高熔融温度（无铅）替代凸点冶金（ABM）形式在晶片上的接合焊盘上形成相对宽的导电平台。

公开(公告)号：US20030068852A1

公开(公告)日：2003-04-10

申请号：US10299135

申请日：2002-11-19

Applicant: Intel Corporation

Inventor： Steven Towle ,  Paul Koning

IPC: H01L021/8238

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2224/82 ,  H01L2924/00

Abstract: A present invention includes a packaging technology that fabricates build-up layers on an encapsulated microelectronic die that has expanded area larger than that of the microelectronic die. An active surface of a microelectronic die is attached by an adhesive material to a protective film sheet to protect the active surface and to control the position of the microelectronic die during an encapsulation process. The protective film sheet has adhesive material substantially only in an area where the microelectronic die and/or a microelectronic package core are attached, or has the adhesive properties of the adhesive material diminished or eliminated in areas where an encapsulation material will be applied.

公开(公告)号：US20030013232A1

公开(公告)日：2003-01-16

申请号：US09903025

申请日：2001-07-11

Applicant: Intel Corporation

Inventor： Steven Towle ,  Hajime Sakamoto ,  Dongdong Wang

IPC: H01L021/44 ,  H01L021/48

CPC classification number: H01L24/19 ,  H01L23/5389 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

Abstract: A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.

Abstract translation: 在承载多个独立电路的半导体晶片上形成钝化层。 钝化层包括露出晶片上的接合焊盘的开口。 然后将导电粘合材料沉积在晶片上，并且可选的保护层沉积在导电粘合材料上。 然后将晶片切割成单独的微电子骰子。 在随后的包装过程中，一个或多个微电子管芯固定在封装芯内以形成管芯/芯组件。 然后在模具/芯组件上形成膨胀的接合垫。 每个模具上的粘合材料增强了扩展的接合焊盘和模具上的钝化材料之间的粘附。 然后将一个或多个金属层在模具/芯组件上构建，以提供例如管芯的端子与封装的外部触点/引线之间的导电连通。

公开(公告)号：US20020158335A1

公开(公告)日：2002-10-31

申请号：US09845896

申请日：2001-04-30

Applicant: Intel Corporation

Inventor： Steven Towle ,  John Tang ,  Gilroy Vandentop

IPC: H01L029/40 ,  H01L023/52 ,  H01L023/48

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/24 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19106 ,  H01L2924/3011 ,  Y10S257/924

Abstract: A low cost technique for packaging microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuit using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core assembly before lamination of the interposer.

Abstract translation: 用于封装微电子电路芯片的低成本技术将芯片固定在封装芯的开口内。 然后在模具/芯组件上形成至少一个金属堆积层，并且将栅格阵列插入单元层叠到堆积层上。 然后可以使用多种安装技术（例如，球栅阵列（BGA），焊盘网格阵列（LGA），引脚网格阵列（PGA），表面贴装技术（SMT）等）中的任何一种将栅格阵列插入单元安装在外部电路内 ）和/或其他）。 在一个实施例中，在层压插入件之前，在模具/芯组件上形成单个堆积层。

公开(公告)号：US20020158334A1

公开(公告)日：2002-10-31

申请号：US09845881

申请日：2001-04-30

Applicant: Intel Corporation

Inventor： Quat T. Vu ,  Tuy T. Ton ,  Steven Towle

IPC: H01L023/02

CPC classification number: H01L23/16 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/2413 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A microelectronic device includes a microelectronic die having an interfacial metal layer deposited over an active surface thereof to perform a signal distribution function within the device. The microelectronic die is fixed within a package core to form a die/core assembly. One or more metallization layers may then be built up over the die/core assembly as part of a packaging scheme. The interfacial metal layer can be applied either before or after the die is fixed within the package core. In one approach, the interfacial layer is applied during wafer-level processing.

Abstract translation: 微电子器件包括具有沉积在其有效表面上的界面金属层的微电子管芯，以在器件内执行信号分配功能。 微电子管芯固定在封装芯内以形成芯/芯组件。 然后可以将一个或多个金属化层作为包装方案的一部分在模具/芯组件上形成。 界面金属层可以在芯片固定在封装芯内之前或之后施加。 在一种方法中，在晶片级处理期间施加界面层。

公开(公告)号：US20040155325A1

公开(公告)日：2004-08-12

申请号：US10774952

申请日：2004-02-09

Applicant: Intel Corporation

Inventor： Qing Ma ,  Harry H. Fujimoto ,  Steven Towle ,  John E. Evert

IPC: H01L023/02

CPC classification number: H01L24/83 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/97 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: Microelectronic packages including a microelectronic die disposed within a recess in a heat spreader and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the heat spreader to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die within the heat spreader. In another embodiment, a microelectronic die is disposed on a heat spreader which has a filler material disposed therearound and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the filler material to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die on the heat spreader.

Abstract translation: 然后在微电子管芯和散热器上制造微电子封装，其中包括设置在散热器的凹槽内的微电子管芯和介电材料和导电迹线的堆积层，以形成微电子封装，以及制造相同的方法 包括在散热器内对准微电子管芯的方法。 在另一个实施例中，微电子管芯设置在散热器上，散热器具有布置在其周围的填充材料，然后在微电子管芯和填充材料上制造介电材料和导电迹线层，形成微电子封装，以及方法 用于制造它们，包括在散热器上对准微电子管芯的方法。

公开(公告)号：US20020167804A1

公开(公告)日：2002-11-14

申请号：US09854539

申请日：2001-05-14

Applicant: Intel Corporation

Inventor： Steven Towle

IPC: H01F003/04 ,  H01F007/06 ,  H05K001/18 ,  H05K003/30

CPC classification number: H01L23/295 ,  H01L21/563 ,  H01L24/19 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/15174 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2924/00

Abstract: An encapsulation material for use within a microelectronic device includes a polymeric base resin that is filled with a fibrous reinforcement material. The fiber reinforcement of the encapsulation material provides an enhanced level of crack resistance within a microelectronic device to improve the reliability of the device. In one embodiment, a fiber reinforced encapsulation material is used to fix a microelectronic die within a package core to form a die/core assembly upon which one or more metallization layers can be built. By reducing or eliminating the likelihood of cracks within the encapsulation material of the die/core assembly, the possibility of electrical failure within the microelectronic device (e.g., within the build up metallization layers) is also reduced.

Abstract translation: 用于微电子器件的封装材料包括填充有纤维增强材料的聚合物基础树脂。 封装材料的纤维增强在微电子器件中提供了增强的抗裂性，以提高器件的可靠性。 在一个实施例中，使用纤维增强的封装材料将微电子管芯固定在封装芯内以形成其上可以构建一个或多个金属化层的管芯/芯组件。 通过减少或消除模具/芯组件的封装材料内的裂缝的可能性，微电子器件内的电气故障的可能性（例如，在积层金属化层内）也被减少。