Invention Application
- Patent Title: MULTILAYER WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
- Patent Title (中): 多层布线基板及其制造方法
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Application No.: US13324535Application Date: 2011-12-13
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Publication No.: US20120153463A1Publication Date: 2012-06-21
- Inventor: Shinnosuke MAEDA
- Applicant: Shinnosuke MAEDA
- Applicant Address: JP Nagoya-shi
- Assignee: NGK SPARK PLUG CO., LTD.
- Current Assignee: NGK SPARK PLUG CO., LTD.
- Current Assignee Address: JP Nagoya-shi
- Priority: JP2010-280320 20101216; JP2011-240394 20111101
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H05K1/00 ; H05K3/10 ; H05K1/11

Abstract:
To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.
Public/Granted literature
- US08946906B2 Multilayer wiring substrate and method of manufacturing the same Public/Granted day:2015-02-03
Information query
IPC分类: