公开(公告)号：US20110232951A1

公开(公告)日：2011-09-29

申请号：US13070094

申请日：2011-03-23

Applicant: Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

IPC: H05K1/09

CPC classification number: H05K3/244 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/099 ,  H05K2203/0361 ,  H01L2924/00

Abstract: In a wiring laminate portion of a multilayer wiring substrate, a solder resist layer having a plurality of openings is disposed on a main surface side of the laminate structure, and connection terminals are embedded in an outermost resin insulation layer in contact with the solder resist layer. Each of the connection terminals comprises a copper layer and a metallic layer formed of at least one type of metal other than copper. A main-surface-side circumferential portion of the copper layer is covered by the solder resist layer. At least a portion of the metallic layer is located in a recess in a main-surface-side central portion of the copper layer. At least a portion of the metallic layer is exposed via a corresponding opening.

Abstract translation: 在多层布线基板的布线层叠部分中，具有多个开口的阻焊层设置在层叠结构的主表面侧，并且连接端子嵌入在与阻焊层接触的最外层树脂绝缘层中 。 每个连接端子包括铜层和由铜以外的至少一种类型的金属形成的金属层。 铜层的主表面侧圆周部分被阻焊层覆盖。 金属层的至少一部分位于铜层的主表面侧中央部的凹部中。 金属层的至少一部分经由相应的开口露出。

公开(公告)号：US20120102732A1

公开(公告)日：2012-05-03

申请号：US13281735

申请日：2011-10-26

Applicant: Shinnosuke MAEDA

Inventor： Shinnosuke MAEDA

IPC: H05K3/04

CPC classification number: H05K3/4682 ,  H01L21/4857 ,  H05K3/0026 ,  H05K2201/0358 ,  H05K2203/0228 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49156

Abstract: A method of manufacturing a multilayer wiring substrate is provided. A foil of a metal-foil-clad resin insulation material is brought into contact with a foil of a metal-foil-clad support substrate. A peripheral edge portion of the resin insulation material exposed as a result of removal of a peripheral edge portion of the foil is adhered to the foil of the support substrate. A plurality of conductor layers and a plurality of resin insulation layers are laminated so as to obtain a laminate structure having a wiring laminate portion, which is to become the multilayer wiring substrate. The laminate structure is cut along a boundary between the wiring laminate portion and a surrounding portion, and the surrounding portion is removed. The wiring laminate portion is separated from the support substrate along the boundary between the two foils.

Abstract translation: 提供一种制造多层布线基板的方法。 使金属箔包覆的树脂绝缘材料的箔与覆盖金属箔的支撑衬底的箔接触。 由于去除箔的周缘部而露出的树脂绝缘材料的周边部分被粘附到支撑基板的箔上。 层叠多个导体层和多个树脂绝缘层，以获得具有将成为多层布线基板的布线层叠部分的层叠结构。 层叠结构沿着布线层压体部分和周围部分之间的边界被切割，并且周围部分被去除。 布线层叠部分沿着两个箔片之间的边界与支撑基板分离。

公开(公告)号：US20110209910A1

公开(公告)日：2011-09-01

申请号：US13034792

申请日：2011-02-25

Applicant: Shinnosuke MAEDA ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Satoshi HIRANO

IPC: H05K1/11 ,  H01R9/00

CPC classification number: H05K3/4682 ,  H05K1/112 ,  H05K3/205 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/099 ,  Y10T29/49147

Abstract: A multilayered wiring board having a stack structure multilayered by alternately stacking a plurality of conductor layers and a plurality of resin insulation layers, wherein a solder resist is provided on at least one of a first main surface side and a second main surface side of the stack structure, a plurality of openings are formed in an outermost resin insulation layer that contacts with the solder resist, a plurality of the first main surface side connecting terminals or a plurality of the second main surface side connecting terminals being made of a copper layer as a main component and positioned in a plurality of the openings, terminal outer surfaces being positioned inwardly from an outer surface of the outermost resin insulation layer, and the solder resist extends into the plurality of openings and makes contact with an outer circumference portion of each of the terminal outer surfaces.

Abstract translation: 一种多层布线基板，其具有通过交替堆叠多个导体层和多个树脂绝缘层而叠层的叠层结构，其中在所述堆叠的第一主表面侧和第二主表面侧中的至少一个上设置阻焊剂 结构中，在与阻焊剂接触的最外层树脂绝缘层中形成多个开口，多个第一主表面侧连接端子或多个第二主表面侧连接端子由铜层制成， 主要部件并且定位在多个开口中，端子外表面从最外层树脂绝缘层的外表面向内定位，并且阻焊剂延伸到多个开口中并与每个的外周部分接触 端子外表面。

公开(公告)号：US20110200788A1

公开(公告)日：2011-08-18

申请号：US13028588

申请日：2011-02-16

Applicant: Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Satoshi HIRANO

IPC: B32B3/24 ,  H05K3/06

CPC classification number: H05K3/4682 ,  H05K1/112 ,  H05K3/205 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/099 ,  Y10T428/24331 ,  Y10T428/24339

Abstract: A plurality of openings are formed in a resin insulation layer on a bottom surface side of a wiring laminate portion which constitutes a multilayer wiring substrate. A plurality of motherboard connection terminals are disposed to correspond to the openings. The motherboard connection terminals are primarily comprised of a copper layer, and peripheral portions of terminal outer surfaces thereof are covered by the outermost resin insulation layer. A dissimilar metal layer made of at least one metal which is lower in etching rate than copper is formed between an inner main surface of the outermost resin insulation layer and peripheral portions of the terminal outer surfaces.

Abstract translation: 在构成多层布线基板的布线层叠体的底面侧的树脂绝缘层上形成有多个开口部。 多个主板连接端子被设置成对应于这些开口。 母板连接端子主要由铜层构成，其端子外表面的周边部分被最外层树脂绝缘层覆盖。 在最外层树脂绝缘层的内主表面和端子外表面的周边部分之间形成由蚀刻速率低于铜的至少一种金属制成的异种金属层。

公开(公告)号：US20110156272A1

公开(公告)日：2011-06-30

申请号：US12976427

申请日：2010-12-22

Applicant: Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

IPC: H01L23/48

CPC classification number: H05K3/3452 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09527 ,  H05K2201/099 ,  H05K2203/0346 ,  H05K2203/0369 ,  H01L2924/00

Abstract: A multilayered wiring substrate, comprising: a plurality of first main surface side connecting terminals arranged in a first main surface of a stack structure; and a plurality of second main surface side connecting terminals being arranged in a second main surface of the stack structure; wherein a plurality of conductor layers are alternately formed in a plurality of stacked resin insulation layers and are operably connected to each other through via conductors tapered such that diameters thereof are widened toward the first or the second main surface, wherein a plurality of openings are formed in an exposed outermost resin insulation layer in the second main surface, and terminal outer surfaces of the second main surface side connecting terminals arranged to match with the plurality of the openings are positioned inwardly from an outer main surface of the exposed outermost resin insulation layer, and edges of terminal inner surfaces are rounded.

Abstract translation: 一种多层布线基板，包括：布置在堆叠结构的第一主表面中的多个第一主表面侧连接端子; 并且多个第二主表面侧连接端子布置在所述堆叠结构的第二主表面中; 其中多个导体层交替地形成在多个堆叠的树脂绝缘层中，并且通过锥形的通孔导体可操作地连接，使得其直径朝向第一或第二主表面加宽，其中形成多个开口 在第二主表面中暴露的最外层树脂绝缘层中，并且布置成与多个开口相匹配的第二主表面侧连接端子的端子外表面从暴露的最外层树脂绝缘层的外主表面位于内侧， 并且端子内表面的边缘是圆形的。

公开(公告)号：US20120153463A1

公开(公告)日：2012-06-21

申请号：US13324535

申请日：2011-12-13

Applicant: Shinnosuke MAEDA

Inventor： Shinnosuke MAEDA

IPC: H01L23/498 ,  H05K1/00 ,  H05K3/10 ,  H05K1/11

CPC classification number: H01L23/5226 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/0035 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49155

Abstract: To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.

Abstract translation: 为了提供通孔导体的连接可靠性提高的多层布线基板，在将下导体层与上导体层隔离的树脂层间绝缘层中形成通孔，并且通孔形成在用于连接的通孔中 下导体层和上导体层。 树脂层间绝缘层的表面是粗糙表面，并且通孔在树脂层间绝缘层的粗糙表面开口。 步进部分形成在通孔周围的打开边缘区域中，使得阶梯部分从围绕开口边缘区域的周边区域凹陷。 阶梯部分的表面粗糙度高于外围区域。

公开(公告)号：US20100208437A1

公开(公告)日：2010-08-19

申请号：US12706255

申请日：2010-02-16

Applicant: Shinnosuke MAEDA ,  Toshiya ASANO ,  Takuya HANDO

Inventor： Shinnosuke MAEDA ,  Toshiya ASANO ,  Takuya HANDO

IPC: H05K7/00 ,  H05K1/09 ,  H05K3/10

CPC classification number: H05K3/243 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/30107 ,  H05K1/0269 ,  H05K1/113 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/3436 ,  H05K3/4682 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/1184 ,  H05K2203/1476 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer wiring substrate of the present invention has a laminated structure composed of conductor layers and resin insulating layers stacked alternately. A plurality of surface connection terminals to which terminals of a chip component are to be surface-connected are formed on a main face of the laminated structure. A plurality of via conductors connected to the plurality of surface connection terminals are formed in the resin insulating layers. Each of the plurality of surface connection terminals has a structure in which a copper layer, a nickel layer, and a gold layer are stacked in this sequence. The gold layer is larger in diameter than at least the copper layer. The gold layer has an overhanging portion which extends radially outward from a circumference of the copper layer.

Abstract translation: 本发明的多层布线基板具有由交替堆叠的导体层和树脂绝缘层构成的层叠结构。 在层压结构的主面上形成有多个芯片部件的端子要被表面连接的表面连接端子。 连接到多个表面连接端子的多个通孔导体形成在树脂绝缘层中。 多个表面连接端子中的每一个具有这样的结构，其中铜层，镍层和金层以该顺序堆叠。 金层的直径比至少铜层大。 金层具有从铜层的圆周向外延伸的突出部分。

公开(公告)号：US20100078786A1

公开(公告)日：2010-04-01

申请号：US12568185

申请日：2009-09-28

Applicant: Shinnosuke MAEDA

Inventor： Shinnosuke MAEDA

IPC: H01L23/02

CPC classification number: H01L23/3128 ,  H01L23/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A wiring substrate assembly includes a resin wiring substrate and a reinforcement member. The resin wiring substrate does not have a core substrate, and includes a substrate main surface, a substrate back surface, a laminate structure comprised of resin insulation layers and conductive layers, and connection terminals disposed on the substrate main surface, to which a chip component is connectable. The reinforcement member is bonded to the substrate main surface and defines an opening portion extending through the reinforcement member so as to expose the main-surface-side connection terminals. The reinforcement member comprises a composite material including a resin material containing an inorganic material.

Abstract translation: 布线基板组件包括树脂布线基板和加强件。 树脂布线基板不具有芯基板，并且包括基板主表面，基板背面，由树脂绝缘层和导电层构成的层叠结构，以及设置在基板主表面上的连接端子，芯片部件 是可连接的 加强构件结合到基板主表面并且限定延伸穿过加强构件的开口部，以暴露主表面侧连接端子。 加强构件包括包含含有无机材料的树脂材料的复合材料。

公开(公告)号：US20120024582A1

公开(公告)日：2012-02-02

申请号：US13195290

申请日：2011-08-01

Applicant: Shinnosuke MAEDA ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Satoshi HIRANO

IPC: H05K1/00

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4015 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/10977 ,  H05K2201/2009 ,  H05K2203/041 ,  H01L2924/00

Abstract: A multilayer wiring substrate includes a laminate structure in which resin insulation layers and conductor layers are alternately laminated. The resin insulation layers include first-type resin insulation layers, and second-type resin insulation layers, each of which contains an inorganic material in a larger amount and is smaller in thermal expansion coefficient as compared with first-type resin insulation layers. On a cross section of the laminate structure taken along a thickness direction thereof, the ratio of a total thickness of the second-type resin insulation layers located in an area A2 to a thickness corresponding to the area A2 is greater than the ratio of a total thickness of the second-type resin insulation layers located in an area A1 to a thickness corresponding to the area A1. The laminate structure is warped such that the laminate structure is convex toward the side where the second main face is present.

Abstract translation: 多层布线基板包括层叠结构，其中树脂绝缘层和导体层交替层叠。 树脂绝缘层包括第一类树脂绝缘层和第二类树脂绝缘层，其中第二类树脂绝缘层与第一类型树脂绝缘层相比，其中含有大量的无机材料并且热膨胀系数较小。 在沿其厚度方向截取的层叠结构的横截面上，位于A2区域中的第二类树脂绝缘层的总厚度与对应于区域A2的厚度的比率大于总共 位于区域A1中的第二类型树脂绝缘层的厚度为对应于区域A1的厚度。 层压结构翘曲，使得层压结构向第二主面存在的一侧凸出。

公开(公告)号：US20110284269A1

公开(公告)日：2011-11-24

申请号：US13109521

申请日：2011-05-17

Applicant: Shinnosuke MAEDA ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Satoshi HIRANO

IPC: H05K1/09

CPC classification number: H05K1/113 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/4682 ,  H05K2201/09472

Abstract: To provide a multilayer wiring substrate which can prevent migration of copper between wiring traces to thereby realize a higher degree of integration, a solder resist layer 25 having a plurality of openings 35, 36 is disposed on a top surface 31 side, and IC-chip connection terminals 41 and capacitor connection terminals 42 are buried in an outermost resin insulation layer 23 in contact with the solder resist layer 25. Each of the IC-chip connection terminals 41 and the capacitor connection terminals 42 is composed of a copper layer 44 and a plating layer 46 covering the outer surface of the copper layer 44. A conductor layer 26 present at the interface between the solder resist layer 25 and the resin insulation layer 23 is composed of a copper layer 27 and a nickel plating layer 28 covering the outer surface of the copper layer 27.

Abstract translation: 为了提供能够防止布线迹线之间的铜迁移从而实现更高的集成度的多层布线基板，具有多个开口部35,36的阻焊层25设置在顶面31侧，IC芯片 连接端子41和电容器连接端子42埋在与阻焊层25接触的最外层树脂绝缘层23中。每个IC芯片连接端子41和电容器连接端子42由铜层44和 镀覆层46覆盖铜层44的外表面。存在于阻焊层25和树脂绝缘层23之间的界面处的导体层26由铜层27和覆盖外表面的镀镍层28构成 的铜层27。