Invention Application
US20150221609A1 METHODS OF FORMING ULTRA THIN PACKAGE STRUCTURES INCLUDING LOW TEMPERATURE SOLDER AND STRUCTURES FORMED THERBY
审中-公开
形成超低密度包装结构的方法，包括低温焊料和形成的结构
- Patent Title: METHODS OF FORMING ULTRA THIN PACKAGE STRUCTURES INCLUDING LOW TEMPERATURE SOLDER AND STRUCTURES FORMED THERBY
- Patent Title (中): 形成超低密度包装结构的方法，包括低温焊料和形成的结构
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Application No.: US14686177Application Date: 2015-04-14
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Publication No.: US20150221609A1Publication Date: 2015-08-06
- Inventor: Sriram Srinivasan , Ram S. Viswanath , Paul R. Start , Rajen S. Sidhu , Rajasekaran Swaminathan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/367 ; H01L23/498
Abstract:
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.
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Information query
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