Invention Application
- Patent Title: PACKAGE WITH LOW STRESS REGION FOR AN ELECTRONIC COMPONENT
- Patent Title (中): 用于电子元件的低应力区域的封装
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Application No.: US14596888Application Date: 2015-01-14
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Publication No.: US20160204089A1Publication Date: 2016-07-14
- Inventor: PAIGE M. HOLM , VIJAY SARIHAN
- Applicant: FREESCALE SEMICONDUCTOR, INC.
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L23/00 ; H01L43/12 ; H01L43/06 ; H01L43/04

Abstract:
A device package includes a substrate having an active surface. Electrical connection bumps are deposited on the active surface and are arranged in an array having a perimeter. At least one electronic component is formed at a region of the active surface, where the region is located outside of the perimeter of the array of electrical connection bumps. When the device package is coupled with external circuitry via the electrical connection bumps, the region at which the electronic component is formed is suspended over the electronic circuitry. This region is subject to a lower stress profile than a region of the active surface circumscribed by the perimeter. Thus, stress sensitive electronic components can be located in this lower stress region of the active surface.
Public/Granted literature
- US09818712B2 Package with low stress region for an electronic component Public/Granted day:2017-11-14
Information query
IPC分类: