Invention Application
- Patent Title: STRUCTURE TO REDUCE BACKSIDE SILICON DAMAGE
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Application No.: US15671647Application Date: 2017-08-08
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Publication No.: US20170355598A1Publication Date: 2017-12-14
- Inventor: Chung-Yen Chou , Chih-Jen Chan , Chia-Shiung Tsai , Ru-Liang Lee , Yuan-Chih Hsieh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: B81C1/00
- IPC: B81C1/00 ; B81B7/00

Abstract:
An integrated circuit (IC) device is provided. The IC device includes a first die including a first substrate and a second die including a second substrate. A plasma-reflecting layer is included on an upper surface of the first die. The plasma-reflecting layer is configured to reflect a plasma therefrom. The second substrate is bonded to the first die so as to form a cavity, wherein a lower surface of the cavity is lined by the plasma-reflecting layer. A dielectric protection layer is present on a lower surface of the second die and lines the upper surface of the cavity. A material of the second substrate has a first etch rate for the plasma and a material of the dielectric protection layer has a second etch rate for the plasma. The second etch rate is less than the first etch rate.
Public/Granted literature
- US10138118B2 Structure to reduce backside silicon damage Public/Granted day:2018-11-27
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