Invention Application
- Patent Title: Vertical Transistor, Integrated Circuitry, Method Of Forming A Vertical Transistor, And Method Of Forming Integrated Circuitry
-
Application No.: US17027046Application Date: 2020-09-21
-
Publication No.: US20220093617A1Publication Date: 2022-03-24
- Inventor: Hung-Wei Liu , Vassil N. Antonov , Ashonita A. Chavan , Darwin Franseda Fan , Jeffery B. Hull , Anish A. Khandekar , Masihhur R. Laskar , Albert Liao , Xue-Feng Lin , Manuj Nahar , Irina V. Vasilyeva
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: H01L27/11514
- IPC: H01L27/11514 ; H01L27/11507 ; H01L29/78 ; H01L21/223 ; H01L27/11597 ; H01L27/1159 ; H01L29/10 ; H01L29/66

Abstract:
A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
Public/Granted literature
Information query
IPC分类: