公开(公告)号：US20250089318A1

公开(公告)日：2025-03-13

申请号：US18954114

申请日：2024-11-20

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Kamal M. Karda ,  Michael Mutch ,  Hung-Wei Liu ,  Jeffery B. Hull

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

公开(公告)号：US11695071B2

公开(公告)日：2023-07-04

申请号：US17159594

申请日：2021-01-27

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Michael Mutch

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L21/02 ,  H01L29/04 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/36 ,  H01L29/66666

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. A gate is operatively laterally-adjacent the channel region. The top source/drain region, the bottom source/drain region, and the channel region respectively have crystal grains and grain boundaries between immediately-adjacent of the crystal grains. At least one of the bottom source/drain region and the channel region has an internal interface there-within between the crystal grains that are above the internal interface and the crystal grains that are below the internal interface. At least some of the crystal grains that are immediately-above the internal interface physically contact at least some of the crystal grains that are immediately-below the internal interface. All of the grain boundaries that are between immediately-adjacent of the physically-contacting crystal grains that are immediately-above and that are immediately-below the interface align relative one another. The internal interface comprises at least one of (a) and (b), where (a): conductivity-modifying dopant concentration immediately-above the internal interface is lower than immediately-below the internal interface and (b): a laterally-discontinuous insulative oxide. Other embodiments, including method, are disclosed.

公开(公告)号：US20220344468A1

公开(公告)日：2022-10-27

申请号：US17860325

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Kamal M. Karda ,  Michael Mutch ,  Hung-Wei Liu ,  Jeffery B. Hull

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

公开(公告)号：US11018229B2

公开(公告)日：2021-05-25

申请号：US16121928

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Manuj Nahar

IPC: H01L29/161 ,  H01L29/04 ,  H01L29/786 ,  H01L21/02 ,  C30B25/18 ,  H01L27/105

Abstract: A method of forming a semiconductor structure includes forming a first material over a base material by vapor phase epitaxy. The first material has a crystalline portion and an amorphous portion. The amorphous portion of the first material is removed by abrasive planarization. At least a second material is formed by vapor phase epitaxy over the crystalline portion of first material. The second material has a crystalline portion and an amorphous portion. The amorphous portion of the second material is removed by abrasive planarization. A semiconductor structure formed by such a method includes the substrate, the first material, the second material, and optionally, an oxide material between the first material and the second material. The substrate, the first material, and the second material define a continuous crystalline structure. Semiconductor structures, memory devices, and systems are also disclosed.

公开(公告)号：US10707298B2

公开(公告)日：2020-07-07

申请号：US16121966

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Manuj Nahar ,  Wayne I. Kinney

IPC: H01L21/20 ,  H01L29/04 ,  H01L21/02 ,  H01L29/161 ,  H01L21/324 ,  H01L29/786 ,  H01L27/105

Abstract: A method includes forming a semiconductor structure. The structure includes a first material, a blocking material, a second material in an amorphous form, and a third material in an amorphous form. The blocking material is disposed between the first material and the second material. At least the second material and the third material each comprise silicon and/or germanium. The structure is exposed to a temperature above a crystallization temperature of the third material and below a crystallization temperature of the second material. Semiconductor structures, memory devices, and systems are also disclosed.

公开(公告)号：US20190066917A1

公开(公告)日：2019-02-28

申请号：US15691541

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Ashonita A. Chavan

IPC: H01G4/10 ,  H01G4/30

Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

公开(公告)号：US12237112B2

公开(公告)日：2025-02-25

申请号：US17950023

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Ashonita A. Chavan

IPC: H01G4/12 ,  H01G4/10 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B51/30 ,  H10B53/30

Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

公开(公告)号：US12191354B2

公开(公告)日：2025-01-07

申请号：US17860325

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Kamal M. Karda ,  Michael Mutch ,  Hung-Wei Liu ,  Jeffery B. Hull

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

公开(公告)号：US20240379739A1

公开(公告)日：2024-11-14

申请号：US18783147

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Manuj Nahar ,  Wayne I. Kinney

IPC: H01L29/04 ,  H01L21/02 ,  H01L21/324 ,  H01L27/105 ,  H01L29/161 ,  H01L29/786

Abstract: A device comprises a first crystalline material, a second material in a substantially crystalline form, a blocking material between the first crystalline material and the second material, and a third material in a substantially crystalline form and adjacent the second material. A crystallization temperature of the third material is different from a crystallization temperature of the second material. At least one of the second material and the third material is substantially free of a grain boundary therein. Also disclosed is a device including a transistor. The transistor comprises a first crystalline material, a substantially continuous crystalline structure, and a blocking material between the first crystalline material and the substantially continuous crystalline structure. The substantially continuous crystalline structure comprises a second crystalline material and a third crystalline material having a different crystallization temperature than the second crystalline material. The substantially continuous crystalline structure is substantially free of a grain boundary therein.

公开(公告)号：US12057472B2

公开(公告)日：2024-08-06

申请号：US18050772

申请日：2022-10-28

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Manuj Nahar ,  Wayne I. Kinney

IPC: H01L29/04 ,  H01L21/02 ,  H01L21/324 ,  H01L29/161 ,  H01L27/105 ,  H01L29/786

CPC classification number: H01L29/04 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/324 ,  H01L29/161 ,  H01L27/105 ,  H01L29/78642

Abstract: A method includes forming a semiconductor structure. The structure includes a first material, a blocking material, a second material in an amorphous form, and a third material in an amorphous form. The blocking material is disposed between the first material and the second material. At least the second material and the third material each comprise silicon and/or germanium. The structure is exposed to a temperature above a crystallization temperature of the third material and below a crystallization temperature of the second material. Semiconductor structures, memory devices, and systems are also disclosed.