Invention Publication
- Patent Title: ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
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Application No.: US17571901Application Date: 2022-01-10
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Publication No.: US20230163082A1Publication Date: 2023-05-25
- Inventor: Chih-Hsien Chiu , Wen-Jung Tsai , Chien-Cheng Lin , Ko-Wei Chang , Yu-Wei Yeh , Shun-Yu Chien , Chia-Yang Chen
- Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
- Applicant Address: TW Taichung City
- Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
- Current Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
- Current Assignee Address: TW Taichung City
- Priority: TW 0143376 2021.11.22
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498 ; H01L23/31

Abstract:
An electronic package is provided in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure is embedded in the packaging layer. Therefore, thermal stress is dispersed through the frame body to avoid warpage of the electronic package, so as to facilitate the arrangement of other electronic components around the electronic component.
Public/Granted literature
- US12057409B2 Electronic package and manufacturing method thereof Public/Granted day:2024-08-06
Information query
IPC分类: