Invention Publication
- Patent Title: INTERCONNECT STRUCTURES
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Application No.: US18451366Application Date: 2023-08-17
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Publication No.: US20240047344A1Publication Date: 2024-02-08
- Inventor: Cyprian Emeka Uzoh , Gaius Gillman Fountain, Jr. , Jeremy Alfred Theil
- Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Applicant Address: US CA San Jose
- Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/00 ; H01L23/29 ; H01L23/31

Abstract:
Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.
Public/Granted literature
- US12125784B2 Interconnect structures Public/Granted day:2024-10-22
Information query
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