公开(公告)号：US12266640B2

公开(公告)日：2025-04-01

申请号：US18513431

申请日：2023-11-17

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

公开(公告)号：US20250006679A1

公开(公告)日：2025-01-02

申请号：US18391173

申请日：2023-12-20

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Jeremy Alfred Theil ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Belgacem Haba ,  Laura Wills Mirkarimi

IPC: H01L23/00

Abstract: A structure includes a first substrate including a first layer having at least one electrically conductive first portion and at least one electrically insulative second portion and a second substrate including a second layer having at least one electrically conductive third portion and at least one electrically insulative fourth portion. The structure further includes an interface layer having at least one electrically conductive oxide material between the first layer and the second layer. The at least one electrically conductive oxide material includes at least one first region between and in electrical communication with the at least one electrically conductive first portion and the at least one electrically conductive third portion, and at least one second region between the at least one electrically insulative second portion and the at least one electrically insulative fourth portion.

公开(公告)号：US20240234159A9

公开(公告)日：2024-07-11

申请号：US18475977

申请日：2023-09-27

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Jeremy Alfred Theil

IPC: H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L23/00

CPC classification number: H01L21/31053 ,  H01L21/0217 ,  H01L21/31111 ,  H01L24/83 ,  H01L2224/83031 ,  H01L2224/83896

Abstract: Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.

公开(公告)号：US11837582B2

公开(公告)日：2023-12-05

申请号：US18148327

申请日：2022-12-29

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Guilian Gao ,  Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/95

Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

公开(公告)号：US20240379607A1

公开(公告)日：2024-11-14

申请号：US18783242

申请日：2024-07-24

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Gaius Gillman Fountain, JR. ,  Chandrasekhar Mandalapu ,  Cyprian Emeka Uzoh ,  Jeremy Alfred Theil

IPC: H01L23/00

Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

公开(公告)号：US12100676B2

公开(公告)日：2024-09-24

申请号：US17559485

申请日：2021-12-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Rajesh Katkar ,  Guilian Gao ,  Laura Wills Mirkarimi

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L2224/08057 ,  H01L2224/08147 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

公开(公告)号：US20230197453A1

公开(公告)日：2023-06-22

申请号：US18066159

申请日：2022-12-14

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Gaius Gillman Fountain, JR. ,  George Carlton Hudson ,  Pawel Mrozek ,  Cyprian Emeka Uzoh ,  Jeremy Alfred Theil

IPC: H01L21/18 ,  H01L21/285 ,  H01L21/288

CPC classification number: H01L21/187 ,  H01L21/28568 ,  H01L21/28556 ,  H01L21/2885

Abstract: Structures and methods for direct bonding are disclosed. A bonded structure can include a first element and a second element. The first element can include a first non-conductive structure that has a non-conductive bonding surface, a cavity that extends at least partially through a thickness of the non-conductive structure from the non-conductive bonding surface, and a first conductive feature that has a first conductive material and a second conductive material over the first conductive material disposed in the cavity. A maximum grain size, in a linear lateral dimension, of the second conductive material can be smaller than 20% of the linear lateral dimension of the conductive feature. There can be less than 20 parts per million (ppm) of impurities at grain boundaries of the second conductive material.

公开(公告)号：US20240379539A1

公开(公告)日：2024-11-14

申请号：US18782629

申请日：2024-07-24

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Gaius Gillman Fountain, JR. ,  Jeremy Alfred Theil

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

公开(公告)号：US20240312951A1

公开(公告)日：2024-09-19

申请号：US18183768

申请日：2023-03-14

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Gaius Gillman Fountain, JR. ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/027 ,  H01L21/56 ,  H01L23/12 ,  H01L25/16

CPC classification number: H01L24/80 ,  H01L21/0273 ,  H01L21/561 ,  H01L23/12 ,  H01L24/03 ,  H01L24/08 ,  H01L24/96 ,  H01L25/162 ,  H01L25/167 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03831 ,  H01L2224/03845 ,  H01L2224/08145 ,  H01L2224/80011 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/96 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043

Abstract: An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.

公开(公告)号：US12046571B2

公开(公告)日：2024-07-23

申请号：US18058693

申请日：2022-11-23

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Cyprian Emeka Uzoh ,  Jeremy Alfred Theil ,  Liang Wang ,  Rajesh Katkar ,  Guilian Gao ,  Laura Wills Mirkarimi

IPC: H01L23/00

CPC classification number: H01L24/26 ,  H01L24/03 ,  H01L24/09 ,  H01L24/27 ,  H01L24/30 ,  H01L24/83 ,  H01L2224/08257 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.