Invention Grant
- Patent Title: Process sequence for doped silicon fill of deep trenches
- Patent Title (中): 深沟槽掺杂硅填充工艺顺序
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Application No.: US11011550Application Date: 2004-12-14
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Publication No.: US07109097B2Publication Date: 2006-09-19
- Inventor: Ajit Paranjpe , Somnath Nag
- Applicant: Ajit Paranjpe , Somnath Nag
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan, LLP
- Main IPC: H01L21/04
- IPC: H01L21/04

Abstract:
A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.
Public/Granted literature
- US20060128139A1 Process sequence for doped silicon fill of deep trenches Public/Granted day:2006-06-15
Information query
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