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    Process sequence for doped silicon fill of deep trenches
    4.
    发明授权
    Process sequence for doped silicon fill of deep trenches 有权
    深沟槽掺杂硅填充工艺顺序

    公开(公告)号：US07109097B2

    公开(公告)日：2006-09-19

    申请号：US11011550

    申请日：2004-12-14

    Applicant: Ajit Paranjpe ,  Somnath Nag

    Inventor： Ajit Paranjpe ,  Somnath Nag

    IPC: H01L21/04

    CPC classification number: C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

    Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

    Abstract translation: 提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，使得从沉积的底部发生膜沉积 向上。 通过这个第一次填充，达到100％以上的步骤覆盖率。 在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充物的沉积速率的沉积速率完成沟槽填充。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。

    POROUS SILICON ELECTRO-ETCHING SYSTEM AND METHOD
    6.
    发明申请
    POROUS SILICON ELECTRO-ETCHING SYSTEM AND METHOD 有权
    多孔硅电蚀刻系统及方法

    公开(公告)号：US20110120882A1

    公开(公告)日：2011-05-26

    申请号：US12688495

    申请日：2010-01-15

    Applicant: Doug Crafts ,  Mehrdad Moslehi ,  Subramanian Tamilmani ,  Joe Kramer ,  George D. Kamian ,  Somnath Nag

    Inventor： Doug Crafts ,  Mehrdad Moslehi ,  Subramanian Tamilmani ,  Joe Kramer ,  George D. Kamian ,  Somnath Nag

    IPC: H01L31/18

    CPC classification number: C25F3/12 ,  C25D11/32 ,  C25F7/00 ,  H01L21/67005 ,  H01L21/67075 ,  H01L21/67086 ,  H01L21/6776 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

    Abstract: It is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high volume production of photovoltaic (PV) solar cell device architecture. It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer.

    Abstract translation: 本发明的一个目的是提供高生产率，低成本的制造设备用于大量生产光伏（PV）太阳能电池器件结构。 本公开的另一个目的是通过使用气相源硅与现有技术相比减少材料加工步骤和材料成本。 本公开教导了制造与气相衬底生长工艺相容的牺牲衬底基底层。 在本公开中使用多孔硅作为牺牲层。 此外，本公开提供了制造牺牲多孔硅PV电池 - 衬底基底层的设备。

    HIGH-PRODUCTIVITY POROUS SEMICONDUCTOR MANUFACTURING EQUIPMENT
    7.
    发明申请
    HIGH-PRODUCTIVITY POROUS SEMICONDUCTOR MANUFACTURING EQUIPMENT 有权
    高效多孔半导体制造设备

    公开(公告)号：US20110030610A1

    公开(公告)日：2011-02-10

    申请号：US12774667

    申请日：2010-05-05

    Applicant: George D. Kamian ,  Somnath Nag ,  Subbu Tamilmani ,  Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Takao Yonehara

    Inventor： George D. Kamian ,  Somnath Nag ,  Subbu Tamilmani ,  Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Takao Yonehara

    IPC: C25F3/12 ,  C25F7/00 ,  C30B19/08 ,  C30B23/06 ,  C30B25/10

    CPC classification number: C25D11/32 ,  C25D11/005 ,  C25D17/001 ,  C25D17/06 ,  C25F3/12 ,  C25F7/00 ,  H01L31/1892 ,  Y02E10/50

    Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further the disclosure is applicable to the general fields of Photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

    Abstract translation: 本公开使得能够高生产率地制造基于半导体的分离层（由单层或多层多孔半导体（例如多孔硅，包括单孔隙率或多孔度层构成），光反射器（由多层/多孔多孔半导体 孔隙度多孔半导体如多孔硅），用于防反射涂层的多孔半导体（例如多孔硅）的形成，钝化层和多结的多带隙太阳能电池（例如，通过形成可变带隙 晶体硅薄膜或晶圆太阳能电池上的多孔硅发射器）。 其他应用包括制造用于脱模和MEMS器件制造，膜形成和浅沟槽隔离（STI）多孔硅的MEMS分离和牺牲层（使用具有最佳孔隙率并随后氧化的多孔硅形成）。 此外，本公开可应用于光伏，MEMS（包括传感器和致动器）的独立或集成半导体微电子，半导体微电子芯片和光电子学的一般领域。

    METHODS FOR LIQUID TRANSFER COATING OF THREE-DIMENSIONAL SUBSTRATES
    10.
    发明申请
    METHODS FOR LIQUID TRANSFER COATING OF THREE-DIMENSIONAL SUBSTRATES 有权
    三维基质液体转移涂层方法

    公开(公告)号：US20090042320A1

    公开(公告)日：2009-02-12

    申请号：US12193415

    申请日：2008-08-18

    Applicant: David Xuan-Qi Wang ,  Mehrdad M. Moslehi ,  Somnath Nag

    Inventor： David Xuan-Qi Wang ,  Mehrdad M. Moslehi ,  Somnath Nag

    IPC: H01L21/66

    CPC classification number: B01D1/22 ,  H01L21/02617 ,  H01L21/6715 ,  H01L22/12 ,  H01L31/035281 ,  H01L31/046 ,  H01L31/1872 ,  H01L31/1892 ,  H01L31/202 ,  H05K1/0284 ,  H05K3/046 ,  H05K3/1258 ,  H05K3/207 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2203/0126 ,  H05K2203/0528 ,  H05K2203/308 ,  Y02E10/50 ,  Y02P70/521

    Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate. Additional features may include filling the micro cavities of the substrate with a filling material, removing the filling material to expose only the substrate surfaces to be coated, coating the substrate with a layer of liquid coating material, and removing said filling material from the micro cavities of the substrate.

    Abstract translation: 这里公开的方法提供了选择性地涂覆3-D衬底的顶表面或脊，同时避免液体涂覆材料吸收到3-D衬底上的微腔中。 衬底包括通过在模板上形成牺牲层而形成在三维衬底中的孔。 模板包括具有在柱之间的柱和沟槽的模板衬底。 这些步骤包括随后沉积半导体层并选择性地蚀刻牺牲层。 然后，该步骤包括从模板中释放半导体层并使用用于将液体涂覆材料施加到3-D衬底的表面的液体转移涂覆步骤涂覆3-D衬底。 该方法还可以包括通过选择性地涂覆衬底的顶部脊或表面来涂覆3-D衬底。 附加特征可以包括用填充材料填充衬底的微腔，去除填充材料以仅暴露待涂覆的衬底表面，用一层液体涂覆材料涂覆衬底，以及从微孔中移除所述填充材料 的基底。

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