Invention Grant
- Patent Title: Method of manufacturing a semiconductor device by forming plating layers having differing thicknesses
- Patent Title (中): 通过形成具有不同厚度的镀层制造半导体器件的方法
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Application No.: US10923874Application Date: 2004-08-24
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Publication No.: US07163613B2Publication Date: 2007-01-16
- Inventor: Nobuaki Hashimoto
- Applicant: Nobuaki Hashimoto
- Applicant Address: JP Tokyo
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP Tokyo
- Agency: Oliff & Berridge, PLC
- Priority: JP11-039623 19990218
- Main IPC: C25D5/16
- IPC: C25D5/16 ; C25D5/02 ; C25D5/00 ; C25D7/06

Abstract:
There is provided a semiconductor device comprising: a first plating layer formed on one surface of an interconnect pattern; a second plating layer formed within through holes in the interconnect pattern; a semiconductor chip electrically connected to the first plating layer; an anisotropic conductive material provided on the first plating layer; and a conductive material provided on the second plating layer, wherein the first plating layer has appropriate adhesion properties with the anisotropic conductive material, and the second plating layer has appropriate adhesion properties with the conductive material.
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