Invention Grant
- Patent Title: Wafer level electro-optical semiconductor manufacture fabrication mechanism and a method for the same
- Patent Title (中): 晶圆级电光半导体制造机构及其制造方法
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Application No.: US11041952Application Date: 2005-01-26
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Publication No.: US07655997B2Publication Date: 2010-02-02
- Inventor: Bily Wang , Jonnie Chuang , Chuan-Fa Lin , Chi-Wen Hung
- Applicant: Bily Wang , Jonnie Chuang , Chuan-Fa Lin , Chi-Wen Hung
- Applicant Address: TW Hsin Chu
- Assignee: Harvatek Corporation
- Current Assignee: Harvatek Corporation
- Current Assignee Address: TW Hsin Chu
- Agency: Kile Goekjian Reed & McManus PLLC
- Main IPC: H01L27/14
- IPC: H01L27/14

Abstract:
A wafer-level electro-optical semiconductor fabrication mechanism and method for the same which improves upon traditional electro-optical semiconductor grain packaging methods. The present invention electrically connects semiconductor grains to the grains on a top surface of a wafer, this is done by either screen-printing or steel board-printing solder or silver paste onto the wafer. After that, the wafer is processed using the following steps: processing the devices, bonding with wire, packaging the wafer and finally cutting the wafer. Using this method raises the production yield while production times and costs are reduced. The wafer-level electro-optical semiconductor fabrication mechanism comprises: a wafer, an electro-optical semiconductor grain and conductive materials.
Public/Granted literature
- US20060166477A1 Wafer level electro-optical semiconductor manufacture fabrication mechanism and a method for the same Public/Granted day:2006-07-27
Information query
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