Invention Grant
- Patent Title: Memory module with load capacitance added to clock signal input
- Patent Title (中): 负载电容加到时钟信号输入的存储模块
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Application No.: US11611036Application Date: 2006-12-14
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Publication No.: US07656744B2Publication Date: 2010-02-02
- Inventor: Yurika Aoki , Seiji Funaba , Yoji Nishio
- Applicant: Yurika Aoki , Seiji Funaba , Yoji Nishio
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2005-362005 20051215
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.
Public/Granted literature
- US20070140040A1 MEMORY MODULE Public/Granted day:2007-06-21
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