公开(公告)号：US09960710B2

公开(公告)日：2018-05-01

申请号：US14240811

申请日：2012-07-19

Applicant: Masashige Tsuji ,  Yasuo Noto ,  Seiji Funaba

Inventor： Masashige Tsuji ,  Yasuo Noto ,  Seiji Funaba

IPC: B60R16/02 ,  H02M7/42 ,  H02M7/537 ,  H02M7/00 ,  B60L11/18

CPC classification number: H02M7/537 ,  B60L11/1803 ,  B60R16/02 ,  H02M7/003 ,  H02M7/42

Abstract: In an automotive vehicle inverter control apparatus of the related art, a limp-home mode is provided, but six power sources including transformers are required for respective gate circuits of the respective IGBT drive circuits. Therefore, a reduction in size and a reduction in weight cannot be achieved, and a demand of the improvement of mountability or the improvement of fuel consumption as described above cannot be satisfied. A power semiconductor module and the drive circuit include three unit semiconductor modules and three unit drive circuits corresponding to a three-phase alternating current, and power supply units of the unit drive circuits are provided independently, whereby the limp-home mode is provided and in addition, the number of power supply units may be reduced, so that the reduction in size and the reduction in weight are achieved.

公开(公告)号：US08456866B2

公开(公告)日：2013-06-04

申请号：US13213239

申请日：2011-08-19

Applicant: Seiji Funaba ,  Yasuo Noto ,  Masashige Tsuji

Inventor： Seiji Funaba ,  Yasuo Noto ,  Masashige Tsuji

IPC: H02M3/335

CPC classification number: H02M1/08 ,  H02M3/335 ,  H02M7/5387 ,  H02M2001/0006 ,  H02M2001/0025 ,  H03K17/04123

Abstract: A power conversion device includes an inverter circuit converting DC power into AC power and including switching devices constituting upper and lower arms, a control circuit controlling the switching devices, a drive circuit driving the switching devices by a signal from the control circuit, and an insulated power supply circuit supplying power to the drive circuit. The control circuit controls a power supply voltage to be outputted from the power supply circuit to the drive circuit. The drive circuit drives the switching devices and based on a carrier frequency and the power supply voltage. The power supply circuit includes a feedback output circuit through which the voltage outputted to the drive circuit is outputted to a power supply control IC. The feedback output circuit includes a dummy load circuit which controls the voltage to be outputted to the power supply control IC based on a change of the carrier frequency.

Abstract translation: 电力转换装置包括将直流电变换为交流电的逆变器电路，包括构成上臂和下臂的开关装置，控制开关装置的控制电路，通过来自控制电路的信号驱动开关装置的驱动电路，以及绝缘 电源电路向驱动电路供电。 控制电路控制从电源电路向驱动电路输出的电源电压。 驱动电路驱动开关器件，并根据载波频率和电源电压。 电源电路包括输出到驱动电路的电压输出到电源控制IC的反馈输出电路。 反馈输出电路包括基于载波频率的变化来控制输出到电源控制IC的电压的虚拟负载电路。

公开(公告)号：US08064222B2

公开(公告)日：2011-11-22

申请号：US12113414

申请日：2008-05-01

Applicant: Yoji Nishio ,  Seiji Funaba

Inventor： Yoji Nishio ,  Seiji Funaba

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H01L23/66 ,  G06F1/184 ,  G06F1/185 ,  G06F1/186 ,  G11C5/025 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/50 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/141 ,  H01L2924/00

Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

Abstract translation: 包括多个堆叠的DRAM芯片的COC DRAM通过使用插入件安装在母板上。 插入器包括Si单元和PCB。 Si单元包括Si基板和布置布线的绝缘层单元。 PCB包括用于Si单元中布线的参考平面。 芯片组和COC DRAM之间的布线结构对于每个信号是相同的。 因此，提供了能够进行高速运转，低功耗，大容量的存储器系统。

公开(公告)号：US20110031939A1

公开(公告)日：2011-02-10

申请号：US12852191

申请日：2010-08-06

Applicant: Seiji Funaba ,  Yasuo Noto ,  Masashige Tsuji

Inventor： Seiji Funaba ,  Yasuo Noto ,  Masashige Tsuji

IPC: H02J7/00

CPC classification number: H02J7/0031 ,  B60K6/445 ,  H02J7/0077 ,  H02J7/045 ,  H02J7/047 ,  H02J9/002 ,  H02M1/36 ,  H02M2001/322 ,  Y02T10/6239

Abstract: A discharge circuit for a DC power supply smoothing capacitor that is used in a power conversion device that supplies DC power via a switch to the DC power supply smoothing capacitor and an inverter, includes; a resistor that discharges charge in the capacitor; a switch connected in series with the resistor, that either passes or intercepts discharge current flowing from the capacitor to the resistor; a measurement circuit that measures a terminal voltage of the capacitor; and a control circuit that controls continuity and discontinuity of the switch; wherein the control circuit, after having made the switch continuous and starting discharge of the capacitor by the resistor, if a terminal voltage of the capacitor as measured by the measurement circuit exceeds a voltage decrease characteristic set in advance, makes the switch discontinuous and stops discharge by the resistor.

Abstract translation: 包括：用于直流电源平滑电容器的放电电路，其用于通过开关向直流电源平滑电容器和逆变器提供直流电力的电力转换装置; 放电电容器中的电荷的电阻器; 与电阻器串联的开关，其通过或截止从电容器流向电阻器的放电电流; 测量电容器的端电压的测量电路; 以及控制电路，其控制开关的连续性和不连续性; 其中，所述控制电路在使所述开关连续地通过所述电阻器连续地开始所述电容器的放电之后，如果由所述测量电路测量的所述电容器的端子电压超过预先设定的电压降低特性，则使所述开关不连续并停止放电 由电阻器。

公开(公告)号：US07768867B2

公开(公告)日：2010-08-03

申请号：US11761470

申请日：2007-06-12

Applicant: Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

Inventor： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

IPC: G11C8/00

CPC classification number: G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

Abstract translation: 叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘 存储芯片12。

公开(公告)号：US20090245424A1

公开(公告)日：2009-10-01

申请号：US12481798

申请日：2009-06-10

Applicant: Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

Inventor： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

IPC: H03K9/00

CPC classification number: H03K5/082 ,  H03K5/135

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract translation: 本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。 本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。 由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收机接收到的数据的状态，并根据保持的状态和输入来调整提取输入数据的定时 数据。 作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。 接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

公开(公告)号：US07558336B2

公开(公告)日：2009-07-07

申请号：US10982946

申请日：2004-11-08

Applicant: Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

Inventor： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

IPC: H03K9/00 ,  H04B3/46 ,  G06K5/04 ,  H03M13/00 ,  G06F13/42

CPC classification number: H03K5/082 ,  H03K5/135

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract translation: 本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。 本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。 由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收器接收到的数据的状态，并且根据保持的状态和输入来调整提取输入数据的定时 数据。 作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。 接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

公开(公告)号：US07478287B2

公开(公告)日：2009-01-13

申请号：US11270608

申请日：2005-11-10

Applicant: Seiji Funaba ,  Yoji Nishio

Inventor： Seiji Funaba ,  Yoji Nishio

IPC: G11B20/20 ,  G01R31/28 ,  G01R31/26

CPC classification number: G11C7/22 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H05K1/0248 ,  H05K1/0268 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09781

Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

Abstract translation: 虚拟布线25用于模拟连接电路板上的半导体集成电路2和6的实际布线26。 半导体集成电路包括能够可变地设置转换速率的数据输出电路28和用于使用虚拟布线25测量信号发送点和信号反射点之间的信号延迟时间的电路29（特征阻抗失配点），并且 由测量电路获得的延迟时间用于确定输出电路的信号转换时间。 信号的转换时间设置为信号发送点和最近端的布线支路之间的信号延迟时间的至少两倍。 以这种方式，实现了由最近端的反射点减轻反射的信号传输。

公开(公告)号：US20070047354A1

公开(公告)日：2007-03-01

申请号：US11511262

申请日：2006-08-29

Applicant: Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu ,  Hideki Osaka

Inventor： Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu ,  Hideki Osaka

IPC: G11C7/02

CPC classification number: G11C5/147 ,  G11C5/02 ,  G11C7/02 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.

Abstract translation: 半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。 第一半导体器件包括第一电极。 第二半导体器件包括第二电极。 参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

公开(公告)号：US07095661B2

公开(公告)日：2006-08-22

申请号：US11019274

申请日：2004-12-23

Applicant: Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba

Inventor： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba

IPC: G11C99/00

CPC classification number: G11C29/028 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/50012

Abstract: There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.

Abstract translation: 存在的问题是，由于DIMM中的C / A信号通过DIMM中的寄存器分配到相应的DRAM，DQ信号直接从DIMM中的端子连接，因此它们的时序难以同步。 提供用于加速高速运行的DIMM的C / A信号的寄存器，寄存器的布线设置为菊花链布线。 然后，通过设置在DRAM中的定时调整电路，根据DRAM的位置而不同的C / A信号和时钟信号之间的布线延迟时间差使得从寄存器的延迟时间之和 并且由于定时调整电路引起的延迟量等于最远的DRAM的延迟时间。