Invention Grant
- Patent Title: Method for fabricating recessed gate MOS transistor device
- Patent Title (中): 凹陷栅极MOS晶体管器件的制造方法
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Application No.: US11696163Application Date: 2007-04-03
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Publication No.: US07679137B2Publication Date: 2010-03-16
- Inventor: Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
- Applicant: Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu
- Priority: TW95114100A 20060420
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L31/062

Abstract:
A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
Public/Granted literature
- US20070246755A1 METHOD FOR FABRICATING RECESSED GATE MOS TRANSISTOR DEVICE Public/Granted day:2007-10-25
Information query
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