公开(公告)号：US20130153982A1

公开(公告)日：2013-06-20

申请号：US13325063

申请日：2011-12-14

Applicant: Shian-Jyh Lin

Inventor： Shian-Jyh Lin

IPC: H01L27/088

CPC classification number: H01L29/792 ,  H01L27/108 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.

公开(公告)号：US08202801B1

公开(公告)日：2012-06-19

申请号：US13400592

申请日：2012-02-21

Applicant: Shian-Jyh Lin

Inventor： Shian-Jyh Lin

IPC: H01L21/44

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L25/0657 ,  H01L2224/94 ,  H01L2225/06544 ,  H01L2924/01019 ,  H01L2924/09701

Abstract: A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.

Abstract translation: 提供了具有低应力的贯通基板通孔。 贯通基板通孔位于基板中。 贯通基板通孔包括：穿过基板的外管; 设置在所述外管内的至少一个内管; 在外管的侧壁上衬有的电介质层和内管的侧壁; 填充内管的强度增强材料; 以及填充外管的导电层。

公开(公告)号：US20110260297A1

公开(公告)日：2011-10-27

申请号：US12767808

申请日：2010-04-27

Applicant: Shian-Jyh Lin ,  Shing-Hwa Renn

Inventor： Shian-Jyh Lin ,  Shing-Hwa Renn

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05087 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method for fabricating a through-substrate via structure. A semiconductor substrate is provided. A first via hole is etched into the semiconductor substrate. A spacer is formed on sidewall of the first via hole. The semiconductor substrate is etched through the first via hole to form a second via hole. The second via hole is wet etched to form a bottle-shaped via hole. An insulating layer is formed lining a lower portion of the bottle-shaped via hole. A first conductive layer is deposited within the bottle-shaped via hole, wherein the first conductive layer define a cavity. A bond pad is formed on a front side of the semiconductor substrate, wherein the bond pad is electrically connected with the first conductive layer. A back side of the semiconductor substrate is polished to reveal the cavity. The cavity is filled with a second conductive layer.

Abstract translation: 一种用于制造贯通基板通孔结构的方法。 提供半导体衬底。 第一通孔被蚀刻到半导体衬底中。 间隔件形成在第一通孔的侧壁上。 通过第一通孔蚀刻半导体衬底以形成第二通孔。 第二通孔被湿蚀刻以形成瓶形通孔。 在瓶状通孔的下部形成有绝缘层。 第一导电层沉积在瓶形通孔内，其中第一导电层限定空腔。 接合焊盘形成在半导体衬底的正面上，其中接合焊盘与第一导电层电连接。 半导体衬底的背面被抛光以露出腔体。 空腔填充有第二导电层。

公开(公告)号：US07955927B2

公开(公告)日：2011-06-07

申请号：US11966891

申请日：2007-12-28

Applicant: Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

Inventor： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC: H01L21/8242

CPC classification number: H01L27/10876 ,  H01L27/10894

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

Abstract translation: 半导体器件包括半导体衬底。 半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。

公开(公告)号：US07923325B2

公开(公告)日：2011-04-12

申请号：US12573076

申请日：2009-10-02

Applicant: Shian-Jyh Lin ,  Chien-Li Cheng

Inventor： Shian-Jyh Lin ,  Chien-Li Cheng

IPC: H01L21/8242

CPC classification number: H01L29/945 ,  H01L27/10823 ,  H01L27/10867 ,  H01L29/66181

Abstract: A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

Abstract translation: 具有单面连接结构的深沟槽装置。 该装置包括其中具有沟槽的衬底。 埋沟槽电容器设置在沟槽的下部。 不对称环形绝缘体设置在沟槽的侧壁的上部。 连接结构设置在沟槽的上部，包括设置在不对称环形绝缘体的相对较低部分上并与其相邻的外延硅层，以及设置在外延硅层和不对称的较高部分之间的连接构件 项圈绝缘子。 导电层设置在不对称环形绝缘体的相对较高和较低的部分之间，以电连接埋入沟槽电容器和连接结构。 盖层设置在连接结构上。 还公开了一种深沟槽器件的制造方法。

公开(公告)号：US20100022065A1

公开(公告)日：2010-01-28

申请号：US12573076

申请日：2009-10-02

Applicant: Shian-Jyh Lin ,  Chien-LI Cheng

Inventor： Shian-Jyh Lin ,  Chien-LI Cheng

IPC: H01L21/02

CPC classification number: H01L29/945 ,  H01L27/10823 ,  H01L27/10867 ,  H01L29/66181

Abstract: A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

Abstract translation: 具有单面连接结构的深沟槽装置。 该装置包括其中具有沟槽的衬底。 埋沟槽电容器设置在沟槽的下部。 不对称环形绝缘体设置在沟槽的侧壁的上部。 连接结构设置在沟槽的上部，包括设置在不对称环形绝缘体的相对较低部分上并与其相邻的外延硅层，以及设置在外延硅层和不对称的较高部分之间的连接构件 项圈绝缘子。 导电层设置在不对称环形绝缘体的相对较高和较低的部分之间，以电连接埋入沟槽电容器和连接结构。 盖层设置在连接结构上。 还公开了一种深沟槽器件的制造方法。

公开(公告)号：US07592229B2

公开(公告)日：2009-09-22

申请号：US11460992

申请日：2006-07-30

Applicant: Shian-Jyh Lin

Inventor： Shian-Jyh Lin

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L21/223 ,  H01L21/28238 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66553

Abstract: A method for fabricating a recessed-gate transistor is disclosed. A trench is recessed into a substrate. A poly/nitride spacer is formed on sidewalls of the trench. A trench bottom oxide is formed. The spacer is then stripped off. A source/drain doping region is formed on the exposed sidewalls of the trench in a self-aligned fashion. The trench bottom oxide is then stripped, thereby forming a curved gate channel.

Abstract translation: 公开了一种用于制造凹陷栅极晶体管的方法。 沟槽凹入基底。 在沟槽的侧壁上形成多晶氮化物间隔物。 形成沟底部氧化物。 然后剥离间隔物。 源/漏掺杂区域以自对准的方式形成在沟槽的暴露的侧壁上。 然后去除沟底部氧化物，从而形成弯曲的栅极通道。

公开(公告)号：US20090146101A1

公开(公告)日：2009-06-11

申请号：US12103681

申请日：2008-04-15

Applicant: Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

Inventor： Chih-Wei Huang ,  Chao-Sung Lai ,  Hsing-Kan Peng ,  Chung-Yuan Lee ,  Shian-Jyh Lin

IPC: C09K13/08

CPC classification number: C23F1/26 ,  H01L21/32134

Abstract: An etchant for etching a metal alloy having hafnium and molybdenum includes 20 to 80 percent by weight of nitric acid, 1 to 49 percent by weight of hydrofluoric acid, 1 to 96 percent by weight of sulfuric acid, and 1 to 30 percent by weight of water, based on the total weight of the etchant.

Abstract translation: 用于蚀刻具有铪和钼的金属合金的蚀刻剂包括20至80重量％的硝酸，1至49重量％的氢氟酸，1至96重量％的硫酸和1至30重量％的 水，基于蚀刻剂的总重量。

公开(公告)号：US20090137093A1

公开(公告)日：2009-05-28

申请号：US12101007

申请日：2008-04-10

Applicant: Shian-Jyh LIN

Inventor： Shian-Jyh LIN

IPC: H01L21/302

CPC classification number: H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a FINFET device includes providing a substrate with a plurality of trench devices arranged in array therein, each of the trench devices comprising a plug protruding above the substrate; forming a plurality of isolation structures along a first direction in the substrate adjacent to the trench devices so as to define an active area exposing the substrate; forming a spacer on each of the plug to define a reactive area between the active area and the spacer; and removing the isolation structures on the reactive area to form a fin structure in the active area.

Abstract translation: 形成FINFET器件的方法包括提供衬底，其中布置有阵列中的多个沟槽器件，每个沟槽器件包括突出在衬底上方的插塞; 在所述衬底中与所述沟槽器件相邻地沿着第一方向形成多个隔离结构，以便限定暴露所述衬底的有源区域; 在所述塞子的每一个上形成间隔件以限定所述有源区域和所述间隔件之间的反应性区域; 以及去除反应性区域上的隔离结构，以在活性区域中形成翅片结构。

公开(公告)号：US20090104748A1

公开(公告)日：2009-04-23

申请号：US12049383

申请日：2008-03-17

Applicant: Shian-Jyh Lin

Inventor： Shian-Jyh Lin

IPC: H01L21/20

CPC classification number: H01L29/66621 ,  H01L27/10867 ,  H01L27/10876 ,  H01L29/4236

Abstract: A method for forming a recess gate trench includes a plurality of trench capacitors formed into a substrate having thereon a pad layer. A portion of the trench top oxide layer of each trench capacitor is etched away to form a hole. The hole is filled with a silicon layer that is coplanar with the pad layer. Shallow trench isolation (STI) structure is formed. A portion of the STI structure is etched away. The pad layer is then stripped. A spacer is formed on a sidewall of the silicon layer. A gate trench is then etched into the substrate in a self-aligned fashion.

Abstract translation: 形成凹槽栅极沟槽的方法包括形成衬底的多个沟槽电容器，其上具有衬垫层。 每个沟槽电容器的沟槽顶部氧化物层的一部分被蚀刻掉以形成孔。 该孔填充有与衬垫层共面的硅层。 形成浅沟槽隔离（STI）结构。 STI结构的一部分被蚀刻掉。 然后剥去垫层。 在硅层的侧壁上形成间隔物。 然后以自对准的方式将栅极沟槽蚀刻到衬底中。