Invention Grant
- Patent Title: Package using array capacitor core
- Patent Title (中): 封装采用阵列电容核心
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Application No.: US11301470Application Date: 2005-12-12
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Publication No.: US07692284B2Publication Date: 2010-04-06
- Inventor: Kimberly D. Eilert , Kaladhar Radhakrishnan , Kemal Aygun , Michael J. Hill
- Applicant: Kimberly D. Eilert , Kaladhar Radhakrishnan , Kemal Aygun , Michael J. Hill
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/52
- IPC: H01L23/52
Abstract:
An embodiment of the present invention is a technique to fabricate a package substrate. The package substrate includes top substrate layers, an array capacitor, and bottom substrate layers. The top substrate layers embed micro-vias. The micro-vias have a micro-via area and provide electrical connections between the top substrate layers. The array capacitor structure is placed in contact with the micro-via area. The array capacitor structure is electrically connected to the micro-vias. The bottom substrate layers are formed on the array capacitor structure.
Public/Granted literature
- US20070134925A1 Package using array capacitor core Public/Granted day:2007-06-14
Information query
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