公开(公告)号：US20080157274A1

公开(公告)日：2008-07-03

申请号：US11648301

申请日：2006-12-29

Applicant: Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

Inventor： Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

IPC: H01L29/00

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/50 ,  H01L23/642 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15787 ,  H05K1/0231 ,  H05K1/0262 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In some embodiments, an individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor is presented. In this regard, an apparatus is introduced having a table-shaped ceramic interposer containing conductive traces, a silicon voltage regulator coupled with contacts on a first surface of the ceramic interposer, and an array capacitor coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，呈现包含陶瓷插入件，硅电压调节器和阵列电容器的单独子组件。 在这方面，引入了具有包含导电迹线的台式陶瓷插入器的装置，与陶瓷插入器的第一表面上的触点耦合的硅电压调节器，以及与陶瓷插入器的第二表面上的触点耦合的阵列电容器 。 还公开并要求保护其他实施例。

公开(公告)号：US20080142962A1

公开(公告)日：2008-06-19

申请号：US12039077

申请日：2008-02-28

Applicant: Brent S. Stone ,  Dustin P. Wood ,  Kaladhar Radhakrishnan

Inventor： Brent S. Stone ,  Dustin P. Wood ,  Kaladhar Radhakrishnan

IPC: H01L23/34 ,  H01L21/02

CPC classification number: H01L23/50 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.

Abstract translation: 集成电路封装包括由衬底的表面支撑的第一电容器和由衬底的表面支撑的第二电容器。 第一电容器在阴影区域内，第二电容器位于阴影阴影区域的外部。

公开(公告)号：US07355836B2

公开(公告)日：2008-04-08

申请号：US11146587

申请日：2005-06-07

Applicant: Kaladhar Radhakrishnan ,  Nicholas L Holmberg ,  Joel A Auernheimer ,  Dustin P Wood

Inventor： Kaladhar Radhakrishnan ,  Nicholas L Holmberg ,  Joel A Auernheimer ,  Dustin P Wood

IPC: H01G4/228

CPC classification number: H01G4/30 ,  H01G4/232

Abstract: An array capacitor is provided. The array capacitor includes a plurality of ground planes inside a dielectric substrate, and a plurality of ground vias. The ground vias electrically connect the ground planes together. Further, the ground vias are connected to ground terminals of the array capacitor to enable electrical coupling between the ground planes and the ground terminals. The array capacitor further includes a plurality of power planes inside the dielectric substrate. The power planes and the ground planes are arranged alternatively inside the dielectric substrate. Each power plane comprises a plurality of power-plane-sections which are mutually electrically isolated. The array capacitor also includes a plurality of power vias which electrically connect the power planes together. Further, the power vias are connected to power terminals of the array capacitor to enable electrical coupling between the power planes and power terminals.

Abstract translation: 提供阵列电容器。 阵列电容器包括介电衬底内的多个接地层，以及多个接地通孔。 接地通孔将接地层电连接在一起。 此外，接地通孔连接到阵列电容器的接地端子，以实现接地层和接地端子之间的电耦合。 阵列电容器还包括介电衬底内的多个电源层。 电源平面和接地平面交替布置在电介质基片内。 每个电力平面包括彼此电隔离的多个电力平面部分。 阵列电容器还包括将电源平面电连接在一起的多个电源通孔。 此外，电源通孔连接到阵列电容器的电源端子，以实现电力平面和电源端子之间的电耦合。

公开(公告)号：US07183644B2

公开(公告)日：2007-02-27

申请号：US10831795

申请日：2004-04-26

Applicant: Dustin P. Wood ,  Kaladhar Radhakrishnan

Inventor： Dustin P. Wood ,  Kaladhar Radhakrishnan

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0262 ,  H05K2201/10325 ,  H05K2201/10719

Abstract: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.

Abstract translation: 集成电路（IC）封装包括安装在基板的第一侧上的基板和IC芯片。 IC封装还包括安装在基板的第二侧上的多个电容器。 第二面与第一面相反。 该IC封装还包括多个导电接触焊盘，其形成在该衬底的第二侧上并散布在该电容器之间。 描述和要求保护其他实施例。

公开(公告)号：US07173804B2

公开(公告)日：2007-02-06

申请号：US10952968

申请日：2004-09-28

Applicant: Kaladhar Radhakrishnan ,  Larry E. Mosley ,  Dustin P. Wood ,  Nicholas L. Holmberg

Inventor： Kaladhar Radhakrishnan ,  Larry E. Mosley ,  Dustin P. Wood ,  Nicholas L. Holmberg

IPC: H01G4/228

CPC classification number: H01G4/232 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/19106 ,  H01L2224/0401

Abstract: An apparatus having a first set of contacts on a first side of the apparatus adapted to interface with a corresponding plurality of contacts on an integrated circuit package. The apparatus further includes a second set of contacts on a second side of the apparatus adapted to interface with a corresponding plurality of grid array leads, and a plurality of capacitive storage structures coupled to the first and second sets of contacts.

Abstract translation: 一种装置，其具有在装置的第一侧上的第一组触点，其适于与集成电路封装上的对应的多个触点相接合。 该装置还包括在该装置的第二侧上的第二组触点，其适于与相应的多个格栅阵列引线相连接，以及耦合到第一和第二组触点的多个电容存储结构。

公开(公告)号：US20050135041A1

公开(公告)日：2005-06-23

申请号：US10744194

申请日：2003-12-22

Applicant: Jung Kang ,  Kaladhar Radhakrishnan ,  Shamala Chikamenahalli

Inventor： Jung Kang ,  Kaladhar Radhakrishnan ,  Shamala Chikamenahalli

IPC: H01L23/522 ,  H01L23/66 ,  H01L25/065 ,  H01L25/16 ,  H01G4/30

CPC classification number: H01L25/0657 ,  H01L23/522 ,  H01L23/66 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/04042 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00

Abstract: An embodiment of the present invention is a technique to integrate passive components in a die assembly. A capacitor, inductor, or resistor is integrated on a spacer between upper and lower dies in stacked dies. Conductors are attached to the capacitor, inductor or resistor to connect the capacitor, inductor, or resistor to at least one of the upper and lower dies.

Abstract translation: 本发明的一个实施例是一种在模具组件中集成无源部件的技术。 电容器，电感器或电阻器集成在堆叠模具中的上模和下模之间的间隔件上。 导体连接到电容器，电感器或电阻器，以将电容器，电感器或电阻器连接到上模具和下模具中的至少一个。

公开(公告)号：US08373074B2

公开(公告)日：2013-02-12

申请号：US12590112

申请日：2009-11-03

Applicant: Peter Hazucha ,  Edward Burton ,  Trang T. Nguyen ,  Gerhard Schrom ,  Fabrice Paillet ,  Kaladhar Radhakrishnan ,  Donald S. Gardner ,  Sung T. Moon ,  Tanay Karnik

Inventor： Peter Hazucha ,  Edward Burton ,  Trang T. Nguyen ,  Gerhard Schrom ,  Fabrice Paillet ,  Kaladhar Radhakrishnan ,  Donald S. Gardner ,  Sung T. Moon ,  Tanay Karnik

IPC: H05K1/16

CPC classification number: H05K1/165 ,  H01L23/645 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K3/42 ,  H05K2201/09627 ,  H05K2201/09709 ,  H01L2924/00

Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.

公开(公告)号：US20080157343A1

公开(公告)日：2008-07-03

申请号：US11648220

申请日：2006-12-29

Applicant: Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

Inventor： Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

IPC: H01L23/13

CPC classification number: H05K1/0262 ,  H01L23/642 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19106 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/0401

Abstract: In some embodiments, a ceramic interposer with silicon voltage regulator and array capacitor combination for integrated circuit packages is presented. In this regard, an apparatus is introduced having a bowl-shaped ceramic interposer containing conductive traces, one or more silicon voltage regulator(s) coupled with contacts on a first surface of the ceramic interposer, and one or more array capacitor(s) coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，提供了具有用于集成电路封装的硅电压调节器和阵列电容器组合的陶瓷插入器。 在这方面，引入了一种装置，其具有包含导电迹线的碗形陶瓷插入器，与陶瓷插入件的第一表面上的触点耦合的一个或多个硅电压调节器，以及一个或多个耦合的阵列电容器 在陶瓷插入件的第二表面上具有触点。 还公开并要求保护其他实施例。

公开(公告)号：US20080002380A1

公开(公告)日：2008-01-03

申请号：US11479626

申请日：2006-06-29

Applicant: Peter Hazucha ,  Edward Burton ,  Trang T. Nguyen ,  Gerhard Schrom ,  Fabrice Paillet ,  Kaladhar Radhakrishnan ,  Donald S. Gardner ,  Sung T. Moon ,  Tanay Karnik

Inventor： Peter Hazucha ,  Edward Burton ,  Trang T. Nguyen ,  Gerhard Schrom ,  Fabrice Paillet ,  Kaladhar Radhakrishnan ,  Donald S. Gardner ,  Sung T. Moon ,  Tanay Karnik

IPC: H05K7/00

CPC classification number: H05K1/165 ,  H01L23/645 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K3/42 ,  H05K2201/09627 ,  H05K2201/09709 ,  H01L2924/00

Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.

Abstract translation: 本文提供了嵌入基板（例如IC封装基板，板基板和/或其他基板）中的电感器和多个电感器。

公开(公告)号：US20070134925A1

公开(公告)日：2007-06-14

申请号：US11301470

申请日：2005-12-12

Applicant: Kimberly Eilert ,  Kaladhar Radhakrishnan ,  Kemal Aygun ,  Michael Hill

Inventor： Kimberly Eilert ,  Kaladhar Radhakrishnan ,  Kemal Aygun ,  Michael Hill

IPC: H01L21/311

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/50 ,  H01L23/66 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/142 ,  H05K1/162 ,  H05K3/007 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/09309 ,  H05K2203/0156 ,  H05K2203/061 ,  H01L2924/00

Abstract: An embodiment of the present invention is a technique to fabricate a package substrate. The package substrate includes top substrate layers, an array capacitor, and bottom substrate layers. The top substrate layers embed micro-vias. The micro-vias have a micro-via area and provide electrical connections between the top substrate layers. The array capacitor structure is placed in contact with the micro-via area. The array capacitor structure is electrically connected to the micro-vias. The bottom substrate layers are formed on the array capacitor structure.

Abstract translation: 本发明的一个实施例是一种制造封装衬底的技术。 封装衬底包括顶部衬底层，阵列电容器和底部衬底层。 顶层衬底层嵌入微通孔。 微通孔具有微通孔区域，并且在顶部基底层之间提供电连接。 阵列电容器结构与微通孔区域接触。 阵列电容器结构电连接到微通孔。 底部衬底层形成在阵列电容器结构上。