Invention Grant
- Patent Title: Capacitor structure having butting conductive layer
- Patent Title (中): 具有对接导电层的电容结构
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Application No.: US11858647Application Date: 2007-09-20
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Publication No.: US07709878B2Publication Date: 2010-05-04
- Inventor: Chung-Chih Chen
- Applicant: Chung-Chih Chen
- Applicant Address: TW Hsinchu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Hsinchu
- Agency: J.C. Patents
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/76 ; H01L29/94 ; H01L31/119

Abstract:
A capacitor structure including a substrate, a butting conductive layer, a second dielectric layer, a plurality of openings, a bottom electrode layer, a capacitor dielectric layer, a top electrode layer, and a second metal interconnect layer is provided. The substrate has a first dielectric layer and a first metal interconnect layer located in the first dielectric layer in a non-capacitor region. The butting conductive layer is disposed over the first dielectric layer in a capacitor region. The second dielectric layer is disposed over the first dielectric layer and covers the butting conductive layer. The openings include a first opening exposing a portion of the butting conductive layer and a second opening exposing the first metal interconnect layer. The bottom electrode layer, the capacitor dielectric layer, and the top electrode layer are conformally stacked in the first opening sequentially. The second metal interconnect layer is disposed in the openings.
Public/Granted literature
- US20090079029A1 CAPACITOR STRUCTURE AND FABRICATING METHOD THEREOF Public/Granted day:2009-03-26
Information query
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