公开(公告)号：US20250169079A1

公开(公告)日：2025-05-22

申请号：US18404839

申请日：2024-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Chau-Chung Hou ,  Yong-Yi Lin ,  Yang-Ju Lu ,  Yu-Lung Shih ,  Ren-Peng Huang ,  Ching-Yang Chuang

IPC: H10B61/00

Abstract: A method of forming a semiconductor structure. A memory structure is formed on a substrate in the memory array region. A dielectric layer is deposited over the memory array region and peripheral region to cover the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the central area of the memory array region, thereby forming an upwardly protruding wall structure along perimeter of the memory array region. The remaining thickness of the dielectric layer in the central area is equal to the sum of a polishing buffer thickness and a target thickness. A first polishing process is performed to remove the upwardly protruding wall structure from the memory array region. A second polishing process is performed to remove upper portion of the dielectric layer with the polishing buffer thickness from the memory array region.

公开(公告)号：US20250157868A1

公开(公告)日：2025-05-15

申请号：US18533191

申请日：2023-12-08

Applicant: United Microelectronics Corp.

Inventor： Chen-Hsiao Wang ,  Kai-Kuang Ho

IPC: H01L23/18 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor structure including a substrate, a pad, a passivation layer, a stress buffer layer, and a bump is provided. The pad is located on the substrate. The passivation layer is located on the substrate. The passivation layer covers a portion of the pad. The stress buffer layer covers the passivation layer. The bump is located on the pad and the stress buffer layer. There is a first recess at an edge of the pad. A bottom surface of the first recess is lower than a top surface of the pad. The stress buffer layer fills the first recess.

公开(公告)号：US12302591B2

公开(公告)日：2025-05-13

申请号：US17882596

申请日：2022-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Linggang Fang

IPC: H10D1/68 ,  H10D1/00 ,  H10D1/66 ,  H10D64/01

Abstract: A method for forming a poly-insulator-poly (PIP) capacitor is disclosed. A semiconductor substrate having a capacitor forming region is provided. A first capacitor dielectric layer is formed on the capacitor forming region. A first poly electrode is formed on the first capacitor dielectric layer. A second capacitor dielectric layer is formed on the first poly electrode. A second poly electrode is formed on the second capacitor dielectric layer. A third poly electrode is formed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is formed between the third poly electrode and the second poly electrode. A fourth poly electrode is formed adjacent to a second sidewall of the second poly electrode that is opposite to the first sidewall. A fourth capacitor dielectric layer is formed between the fourth poly electrode and the second poly electrode.

公开(公告)号：US12300743B2

公开(公告)日：2025-05-13

申请号：US18665600

申请日：2024-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US12300534B2

公开(公告)日：2025-05-13

申请号：US17880685

申请日：2022-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Chee Hau Ng ,  Ching-Yang Wen ,  Purakh Raj Verma

IPC: H01L21/762 ,  H01L21/304 ,  H01L21/768

Abstract: A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.

公开(公告)号：US20250149359A1

公开(公告)日：2025-05-08

申请号：US18395777

申请日：2023-12-26

Applicant: United Microelectronics Corp.

Inventor： Chih-Chung KUO ,  Yung-Chieh KUO ,  Cheng-Tai PENG ,  Min-Wei TSAI ,  Sheng- Ming WANG ,  Jui-Hung LEE ,  Ke-Wei WEI ,  Ping-Yi LU ,  Shi-Hao WANG ,  Chih-Hsiang HSIAO

IPC: H01L21/67

Abstract: A controlling method for semiconductor process auxiliary apparatus, a control assembly and a manufacturing system are provided. The controlling method includes the following steps. At least one manufacturing parameter of a semiconductor manufacturing processing apparatus are obtained. An energy adjusting signal is generated according to the manufacturing parameter. An auxiliary apparatus controlling signal is generated according to the energy adjusting signal. The semiconductor process auxiliary apparatus is controlled according to the semiconductor auxiliary apparatus controlling signal.

公开(公告)号：US20250142854A1

公开(公告)日：2025-05-01

申请号：US18523930

申请日：2023-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rudy Octavius Sihombing ,  Su Xing

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a first gate structure on the HV region and a second gate structure on the LV region, forming a first lightly doped drain (LDD) adjacent to one side of the first gate structure and a second LDD adjacent to another side of the first gate structure, and then forming a third lightly doped drain (LDD) adjacent to one side of the second gate structure and a fourth LDD adjacent to another side of the second gate structure. Preferably, the first LDD and the second LDD are asymmetrical, the third LDD and the fourth LDD are asymmetrical, and the second LDD and the third LDD are symmetrical.

公开(公告)号：US20250142841A1

公开(公告)日：2025-05-01

申请号：US18515299

申请日：2023-11-21

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li

IPC: H01L29/94 ,  H01L29/66 ,  H01L29/786

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first electrode, a second electrode, an insulating layer, a channel layer, a gate dielectric layer, a source electrode and a drain electrode. The first electrode is disposed on a substrate. The second electrode is disposed on the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The channel layer is disposed on the second electrode. The gate dielectric layer is disposed between the channel layer and the second electrode. The source electrode is electrically connected to the first electrode and the channel layer. The drain electrode is electrically connected to the channel layer.

公开(公告)号：US20250138304A1

公开(公告)日：2025-05-01

申请号：US18386619

申请日：2023-11-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao ZHOU

IPC: G02B26/10 ,  G02B26/08

Abstract: A projection system is provided. The projection system includes at least one micro LED line and a scan optical system. The micro LED line is configured for emitting lights with a changing frequency of X times per second. The scan optical system is disposed at a downstream side of the at least one micro LED line. The scan optical system is configured to scan the lights emitted from the micro LED line with a scan rate of M seconds per scan and to project images formed of the lights to corresponding positions on a target projection plane. The projection system has a horizontal resolution of N lines. A total number n of the at least one micro LED line is smaller than N. Also, X=M*(N/n).

公开(公告)号：US12290004B2

公开(公告)日：2025-04-29

申请号：US18674889

申请日：2024-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H01L27/02 ,  H10B61/00

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.