Invention Grant
- Patent Title: Gate-coupled substrate-triggered ESD protection circuit and integrated circuit therewith
- Patent Title (中): 栅极耦合衬底触发ESD保护电路及其集成电路
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Application No.: US11163466Application Date: 2005-10-20
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Publication No.: US07719813B2Publication Date: 2010-05-18
- Inventor: Shiao-Shien Chen
- Applicant: Shiao-Shien Chen
- Applicant Address: TW Hsinchu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Main IPC: H02H9/00
- IPC: H02H9/00
Abstract:
An ESD protection design using a gate-coupled substrate-triggered technique is provided. A required RC time constant maintained in the gate-coupled substrate-triggered ESD circuit is based on a parasitic MOS capacitor and larger resistor, in which a layout area for the substrate-triggered ESD protection design is significantly reduced.
Public/Granted literature
- US20070091530A1 GATE-COUPLED SUBSTRATE-TRIGGERED ESD PROTECTION CIRCUIT AND INTEGRATED CIRCUIT THEREWITH Public/Granted day:2007-04-26
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