Invention Grant
- Patent Title: Design rules checking augmented with pattern matching
- Patent Title (中): 设计规则检查用模式匹配增强
-
Application No.: US11613006Application Date: 2006-12-19
-
Publication No.: US07757190B2Publication Date: 2010-07-13
- Inventor: Vito Dai , Jie Yang , Norma Rodriguez , Luigi Capodieci
- Applicant: Vito Dai , Jie Yang , Norma Rodriguez , Luigi Capodieci
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.
Public/Granted literature
- US20080148211A1 Design Rules Checking Augmented With Pattern Matching Public/Granted day:2008-06-19
Information query