Invention Grant
- Patent Title: Electrical device and method for fabricating the same
- Patent Title (中): 电气装置及其制造方法
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Application No.: US12211815Application Date: 2008-09-17
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Publication No.: US07795090B2Publication Date: 2010-09-14
- Inventor: Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
- Applicant: Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu
- Priority: TW95101275A 20060112
- Main IPC: H01L21/8242
- IPC: H01L21/8242

Abstract:
A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.
Public/Granted literature
- US20090011569A1 ELECTRICAL DEVICE AND METHOD FOR FABRICATING THE SAME Public/Granted day:2009-01-08
Information query
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