Invention Grant
- Patent Title: Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures
- Patent Title (中): 用于在制造互连结构通孔期间监测蚀刻特性的方法和半导体结构
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Application No.: US11875535Application Date: 2007-10-19
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Publication No.: US07829889B2Publication Date: 2010-11-09
- Inventor: Matthias Lehr
- Applicant: Matthias Lehr
- Applicant Address: US TX Austin
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US TX Austin
- Agency: Williams, Morgan & Amerson
- Priority: DE102007015506 20070330
- Main IPC: H01L23/58
- IPC: H01L23/58
Abstract:
By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified.
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