Invention Grant
US07884026B2 Method of fabricating dual damascene structure 有权
双镶嵌结构的制作方法

  • Patent Title: Method of fabricating dual damascene structure
  • Patent Title (中): 双镶嵌结构的制作方法
  • Application No.: US11458689
    Application Date: 2006-07-20
  • Publication No.: US07884026B2
    Publication Date: 2011-02-08
  • Inventor: An-Chi Liu
  • Applicant: An-Chi Liu
  • Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
  • Assignee: United Microelectronics Corp.
  • Current Assignee: United Microelectronics Corp.
  • Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
  • Agent Winston Hsu; Scott Margo
  • Main IPC: H01L21/302
  • IPC: H01L21/302
Method of fabricating dual damascene structure
Abstract:
A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a trench and expose the conductive layer. By operating all procedures within one chamber, manufacturing time is efficiently shortened and yield is thus increased.
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