Invention Grant
US07936184B2 Apparatus and methods for adjusting performance of programmable logic devices
有权
用于调节可编程逻辑器件性能的装置和方法
- Patent Title: Apparatus and methods for adjusting performance of programmable logic devices
- Patent Title (中): 用于调节可编程逻辑器件性能的装置和方法
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Application No.: US11361642Application Date: 2006-02-24
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Publication No.: US07936184B2Publication Date: 2011-05-03
- Inventor: Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
- Applicant: Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Law Offices of Maximilian R. Peterson
- Main IPC: H01L25/00
- IPC: H01L25/00
Abstract:
A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.
Public/Granted literature
- US20070200596A1 Apparatus and methods for adjusting performance of programmable logic devices Public/Granted day:2007-08-30
Information query
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