Process for the simultaneous deposition of crystalline and amorphous layers with doping

Invention Grant

US07947552B2 Process for the simultaneous deposition of crystalline and amorphous layers with doping 有权

Title translation: 用掺杂法同时沉积结晶和非晶层的工艺

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Patent Title: Process for the simultaneous deposition of crystalline and amorphous layers with doping
Patent Title (中): 用掺杂法同时沉积结晶和非晶层的工艺
Application No.: US12106667

Application Date: 2008-04-21
Publication No.: US07947552B2

Publication Date: 2011-05-24
Inventor: Herbert Schäfer , Martin Franosch , Thomas Meister , Josef Böck
Applicant: Herbert Schäfer , Martin Franosch , Thomas Meister , Josef Böck
Applicant Address: DE Neubiberg
Assignee: Infineon Technologies AG
Current Assignee: Infineon Technologies AG
Current Assignee Address: DE Neubiberg
Agency: Eschweiler & Associates, LLC
Main IPC: H01L21/8238
IPC: H01L21/8238

Process for the simultaneous deposition of crystalline and amorphous layers with doping

Abstract:

One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract(Chinese):

本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。沉积包括形成两个或更多个子层。可以为每个单独的子层改变工艺参数以优化沉积特性。

Public/Granted literature

US20090261327A1 PROCESS FOR THE SIMULTANEOUS DEPOSITION OF CRYSTALLINE AND AMORPHOUS LAYERS WITH DOPING Public/Granted day:2009-10-22

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS