Invention Grant
- Patent Title: Wafer level packaging method
- Patent Title (中): 晶圆级封装方法
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Application No.: US12423456Application Date: 2009-04-14
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Publication No.: US07972904B2Publication Date: 2011-07-05
- Inventor: Wen-Jeng Fan
- Applicant: Wen-Jeng Fan
- Applicant Address: TW Hsinchu
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A wafer level packaging method is revealed. Firstly, a wafer with a plurality of bumps disposed on a surface is provided. Placing a dielectric tape on a mold plate is followed. Then, the wafer is laminated with the mold plate to make the dielectric tape be compliantly bonded to the surface of the wafer and to make the bumps be embedded in the dielectric tape. After removing the mold plate, flattening the dielectric tape to form a plurality of exposed surfaces of the bumps wherein the exposed surfaces and the flattened surface of the dielectric tape are coplanar. Therefore, the exposed surfaces of the bumps can be regarded as effective alignment points for easy pattern recognition of the wafer level packaged wafers during singulation process.
Public/Granted literature
- US20100261315A1 WAFER LEVEL PACKAGING METHOD Public/Granted day:2010-10-14
Information query
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