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    Method for forming an isolated inner lead from a leadframe
    1.
    发明授权
    Method for forming an isolated inner lead from a leadframe 有权
    从引线框架形成隔离的内引线的方法

    公开(公告)号：US08240029B2

    公开(公告)日：2012-08-14

    申请号：US12274694

    申请日：2008-11-20

    Applicant: Wen-Jeng Fan ,  Yu-Mei Hsu

    Inventor： Wen-Jeng Fan ,  Yu-Mei Hsu

    IPC: H01R43/00 ,  H01R43/16

    CPC classification number: H01L23/49575 ,  H01L23/4951 ,  H01L23/49558 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    Abstract: A method for forming an isolated inner lead from a leadframe is revealed. The leadframe primarily comprises a plurality of leads, the isolated inner lead, and an external lead. Each lead has an inner portion having a finger. The isolated inner lead having two fingers is completely formed inside a molding area and is made of the same metal leadframe as the leads. One finger of the isolated inner lead and the fingers of the leads are linearly arranged. The other finger of the isolated inner lead is adjacent to a finger of the external lead. At least one of the inner portions divides the isolated inner lead from the external lead. The isolated inner lead is integrally connected to an adjacent one of the inner portions by a connecting block. A tape-attaching step is performed to mechanically connect the isolated inner lead where two insulating tapes are attached in a manner that the connecting block can be removed. Therefore, the isolated inner lead is electrically isolated from the leads and can be mechanically fixed to replace extra redistributing components during semiconductor packaging processes.

    Abstract translation: 揭示了从引线框形成隔离内引线的方法。 引线框架主要包括多个引线，隔离内引线和外引线。 每个引线具有具有手指的内部部分。 具有两个指状物的隔离内部引线在成型区域内完全形成，并且由与引线相同的金属引线框构成。 隔离的内引线和引线的指状物的一个指状物线性排列。 隔离的内引线的另一个手指与外引线的手指相邻。 内部部分中的至少一个将隔离的内部引线与外部引线分开。 隔离的内引线通过连接块一体连接到相邻的一个内部部分。 执行胶带附着步骤以将连接块移除的方式机械地连接隔离的内引线，其中两个绝缘带被附接。 因此，隔离的内部引线与引线电隔离，并且可以机械固定以在半导体封装工艺期间替换额外的再分配组件。

    Semiconductor package with leads on a chip having multi-row of bonding pads
    2.
    发明授权
    Semiconductor package with leads on a chip having multi-row of bonding pads 失效
    带芯片的半导体封装，具有多排焊盘

    公开(公告)号：US07723828B2

    公开(公告)日：2010-05-25

    申请号：US12068613

    申请日：2008-02-08

    Applicant: Wen-Jeng Fan ,  Yu-Mei Hsu

    Inventor： Wen-Jeng Fan ,  Yu-Mei Hsu

    IPC: H01L23/495

    CPC classification number: H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    Abstract: A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.

    Abstract translation: LOC引线框架半导体封装包括具有多排焊盘的芯片。 至少一个母线连接在芯片上，并且设置在第一排接合焊盘和引线的指状物之间。 多个接合线将第一排接合焊盘电连接到引线的指状物。 汇流条附接到芯片的有效表面的部分包括弯曲部分，该弯曲部分远离手指弯曲。 长接合线通过超过弯曲部分将第二排接合焊盘中的一个电线连接到引线的一个指状物。 因此，长接合线和母线之间的距离增加，以避免长接合线和母线之间的电短路并且提高LOC半导体封装的电连接的质量。

    Lead frame for chip packages with wire-bonding at single-side pads
    7.
    发明申请
    Lead frame for chip packages with wire-bonding at single-side pads 审中-公开
    单面贴片引线接线芯片封装引线框架

    公开(公告)号：US20080179720A1

    公开(公告)日：2008-07-31

    申请号：US11657716

    申请日：2007-01-25

    Applicant: Wen-Jeng Fan ,  Yi-Ling Liu

    Inventor： Wen-Jeng Fan ,  Yi-Ling Liu

    IPC: H01L23/495

    CPC classification number: H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2924/00014 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A chip package and a lead frame used in the chip package are disclosed. The lead frame includes a plurality of first side leads and a plurality of second side leads where the first side leads have a plurality of first bent leads extending from a first edge and the second side leads have a plurality of second bent leads extending from a second edge. The inner ends of the first bent leads and the inner ends of the second bent leads are facing to a third edge between the first and second edges and are connected to the lead frame. Therefore, the lengths of the first side leads are equal and symmetrical to the ones of the second side leads without any suspended long leads for chip attachment. The chip package is most suitable for packaging chips with bonding pads on one single side.

    Abstract translation: 公开了一种用于芯片封装的芯片封装和引线框架。 引线框架包括多个第一侧引线和多个第二侧引线，其中第一侧引线具有从第一边缘延伸的多个第一弯曲引线，并且第二侧引线具有多个从第二边引出的第二弯曲引线 边缘。 第一弯曲引线的内端和第二弯曲引线的内端面向第一和第二边缘之间的第三边缘并且连接到引线框架。 因此，第一侧引线的长度与第二侧引线的长度相等且对称，而没有用于芯片附接的任何悬挂的长引线。 芯片封装最适合在一个单面封装具有焊盘的芯片。

    IC package keeping attachment level of leads on chip during molding process
    8.
    发明申请
    IC package keeping attachment level of leads on chip during molding process 审中-公开
    IC封装在成型过程中保持片上引线的附着水平

    公开(公告)号：US20080116547A1

    公开(公告)日：2008-05-22

    申请号：US11600919

    申请日：2006-11-17

    Applicant: Wen-Jeng Fan

    Inventor： Wen-Jeng Fan

    IPC: H01L23/495

    CPC classification number: H01L23/16 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: An IC package keeping the attachment level of leads on chip during molding process, mainly comprises a plurality of leads of a Lead-On-Chip (LOC) leadframe, a chip adhered under the leads, a plurality of bonding wires electrically connecting the chip to the leads, a plurality of first supporting columns disposed above some of the leads, a plurality of second supporting columns disposed under the some of the leads and a molding compound. The molding compound encapsulates the chip, the bonding wires, inner portions of the leads and sides of the first and second supporting columns. Therein, the first and second supporting columns are longitudinally corresponding to each other and adjacent the chip. The thickness including one of the first supporting columns, a corresponding one of the second supporting columns and one of the leads disposed corresponding to the selected first supporting column and the selected second supporting column is approximately as same as that of the molding compound. By means of the supporting columns in the package, it is able to prevent the problems of chip displacement during molding process and exposure of chip backside or the bonding wires.

    Abstract translation: 一种在成型工艺中保持芯片引线附着水平的IC封装，主要包括芯片上引线框架（LOC）的多个引线，引线下方的芯片，将芯片电连接到 引线，设置在一些引线上方的多个第一支撑柱，设置在一些引线下方的多个第二支撑柱和模制化合物。 模塑料封装芯片，接合线，引线的内部和第一和第二支撑柱的侧面。 其中，第一和第二支撑柱纵向对应并且与芯片相邻。 包括第一支撑柱中的一个，相应的一个第二支撑柱和与所选择的第一支撑柱相对应设置的一个引线和所选择的第二支撑柱之间的厚度大致与模塑料的相同。 通过封装中的支撑柱，可以防止模制过程中芯片位移的问题和芯片背面或接合线的暴露。

    Structure of electronic package and printed circuit board thereof
    9.
    发明申请
    Structure of electronic package and printed circuit board thereof 审中-公开
    电子封装及其印刷电路板的结构

    公开(公告)号：US20070252252A1

    公开(公告)日：2007-11-01

    申请号：US11413014

    申请日：2006-04-28

    Applicant: Wen-Jeng Fan

    Inventor： Wen-Jeng Fan

    IPC: H01L23/02

    CPC classification number: H01L23/49816 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/094 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A PCB for mounting IC package is designed with dummy solder pads. Dummy solder pastes will spread on the dummy solder pads after screen printing process of solder paste. A substrate for a package of IC is designed with or without dummy solder pads. After mounting the package of IC onto the PCB, the dummy solder paste may or may not solder to the substrate of the package of IC. When the package of IC suffers external force, the dummy solder pastes can help provide supporting for the package of IC and increase the mechanical strength to avoid package or IC crack.

    Abstract translation: 用于安装IC封装的PCB设计有虚拟焊盘。 在焊膏丝网印刷工艺之后，虚拟焊膏将在虚拟焊盘上铺展。 用于封装IC的衬底被设计为具有或不具有虚拟焊盘。 将IC封装安装到PCB上后，虚拟焊膏可能会焊接到IC封装的衬底上，也可能不会焊接到IC封装的衬底上。 当IC封装受到外力时，虚拟焊膏可以帮助提供对IC封装的支持，并增加机械强度以避免封装或IC裂纹。

    Method for forming an EMI shielding layer on all surfaces of a semiconductor package
    10.
    发明授权
    Method for forming an EMI shielding layer on all surfaces of a semiconductor package 有权
    在半导体封装的所有表面上形成EMI屏蔽层的方法

    公开(公告)号：US08420437B1

    公开(公告)日：2013-04-16

    申请号：US13311063

    申请日：2011-12-05

    Applicant: Wen-Jeng Fan

    Inventor： Wen-Jeng Fan

    IPC: H01L9/00 ,  H01L21/00

    CPC classification number: H01L23/552 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: Disclosed is a method for forming an EMI shielding layer on all surfaces of a semiconductor package in order to enhance EMI shielding effect on all surfaces and to prevent electrical short to external terminals of the semiconductor package. According to the method, a temporary protective layer is formed on the external terminals where the temporary protective layer is further in contact with a plurality of annular surface regions of the semiconductor package surrounding and adjacent to the external terminals. Then, the EMI shielding layer is formed on the top surface, the bottom surface and the side surfaces of the semiconductor package without forming on the external terminals.

    Abstract translation: 公开了一种用于在半导体封装的所有表面上形成EMI屏蔽层的方法，以便增强对所有表面的EMI屏蔽效果，并防止对半导体封装的外部端子的电短路。 根据该方法，在外部端子上形成临时保护层，其中临时保护层与外部端子周围和邻近的半导体封装体的多个环形表面区域进一步接触。 然后，EMI屏蔽层形成在半导体封装的顶表面，底表面和侧表面上，而不形成在外部端子上。

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